A 99-mm/sup 2/ 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system

Kumaki, S.; Takata, H.; Ajioka, Yoshiaki; Ooishi, T.; Ishihara, Kengo; Hanami, A.; Tsuji, T.; Watanabe, Tsugio; Morishima, Chikayoshi; Yoshizawa, T.; Sato, H.; Hattori, Shinichi; Koshio, A.; Tsukamoto, K.; Tsuneo, Matsumura

doi:10.1109/4.987099

Cited by 13 publications

(1 citation statement)

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“…Parallel encoding methods for MPEG-2 video have been intensively studied [3], [4], where fragments of video images are transferred to multiple encoders and inter-chip information exchange is performed. Output concatenation and multiplexing, however, continue to be performed by external devices as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

Onishi

Nakamura

Yoshitome

et al. 2008

IEICE Transactions on Information and Systems

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SUMMARY This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.

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Section: Introductionmentioning

confidence: 99%