A 97mW 0–4GHz 65nm CMOS concurrent receiver

Abstract

Telecommunication industry claims for an increase of data rate. Techniques must sustain this effort especially by achieving several Gpbs transceivers consumming a very low power. A Sampled Analog Signal Processor was developed performing a Fast Fourier transform using voltage samples to challenge this idea. It receives any RF signal from 0 to 5 GHz, whatever the band and modulation schemes. The circuit was designed in 65nm CMOS technology and demonstrates the feasibility of a concurrent reception within a frequency of 0 to 4GHz at a power consumption of 97mW.