A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

Thandri, Bharath Kumar; Silva-Martí­nez, J.

doi:10.1109/tcsii.2006.870217

Cited by 7 publications

(3 citation statements)

References 13 publications

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“…The high-resolution requirement, together with the wide Nyquist bandwidth (on the order of megahertz), which is essential because of the high data rate and the need to avoid aliasing of the interferers onto the down-converted signal, necessitates the use of high-performance ADCs. Among the wide variety of high-resolution ADC architectures, ΔΣ ADCs, with their high tolerance for component mismatches and lower power dissipation, are becoming increasingly popular in wireless receiver applications [2], [3]. However, the presence of interferers puts a severe demand on the linearity requirements of the analog circuitry and also necessitates the use of high-order digital filters to attenuate these interfering signals.…”

Section: Introductionmentioning

confidence: 99%

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities

Pandita

Martin

2009

IEEE Trans. Circuits Syst. II

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To alleviate the image-rejection requirements of the front-end filters and the feedback digital-to-analog converter (DAC) matching requirements, an oversampling complex discretetime (DT) ΔΣ analog-to-digital converter (ADC) with a signaltransfer function that achieves significant filtering of interfering signals is proposed. With a filtering signal transfer function (STF) and stopband attenuation greater than 30 dB, the ΔΣ modulator reduces the intermodulation of the desired signal and the interfering signals at the input of a quantizer, and also avoids feedback of high-frequency interfering signals at the input of the modulator. This filtering of the interfering signals reduces sensitivity to DAC nonlinearities. The reported DT complex ΔΣ ADC is intended for digital television (DTV) receiver applications. With a maximum intended sampling frequency of 128 MHz and an oversampling ratio of 16, the ADC has been designed to support a maximum DTV signal bandwidth of 8 MHz. The IC achieved a 70.9-dB signal-to-noise-and-distortion ratio over a 6-MHz band centered around 3 MHz. The image-rejection ratio of the ΔΣ ADC was measured to be greater than 65 dB. The fabricated chip consumes 122.4 mW and occupies a silicon area of 2.15 mm 2 . Index Terms-AdvancedTelevisions Systems Committee (ATSC), complex ΔΣ modulator, continuous time, digital video broadcasting-terrestrial (DVB-T), dynamic element matching (DEM), intermediate frequency (IF), noise transfer function (NTF), signal transfer function (STF).

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Section: Introductionmentioning

confidence: 99%

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities

Pandita

Martin

2009

IEEE Trans. Circuits Syst. II

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“…Miller and Ahuja compensation are two commonly applied techniques. Feedforward compensation is another approach, which tries to overcome some of the limitations of Miller compensation schemes [1,2]. In literature, some examples can be found where both cascoding and cascading with feedforward compensation can be found (e.g., [1]).…”

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confidence: 99%

“…Feedforward compensation is another approach, which tries to overcome some of the limitations of Miller compensation schemes [1,2]. In literature, some examples can be found where both cascoding and cascading with feedforward compensation can be found (e.g., [1]). We present here an alternative feedforward-based gain-boosting technique which integrates efficiently with a folded-cascode amplifier.…”

mentioning

confidence: 99%

Folded-cascode amplifier with efficient feedforward gain-boosting

2010

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In this letter, an efficient implementation of a two-stage feedforward amplifier is proposed. The new amplifier topology boosts the DC gain of a folded-cascode amplifier by adding a gain path which makes use of the "free" transconductance of the folding current sources. Only a single differential pair is used to convert the input voltage in a current. A current splitter extracts the parts needed for feedforward and for the first gain stage. This turns out to be favorable in terms of noise when compared to more traditional feedforward amplifiers.Introduction Many applications require a higher openloop gain than a basic telescopic-or folded-cascode amplifier (FCA) can provide. In such situations, regulated (active) cascodes are often applied. Alternatively, one can turn to cascading, resulting in a second-order system which needs compensation. Miller and Ahuja compensation are two commonly applied techniques. Feedforward compensation is another approach, which tries to overcome some of the limitations of Miller compensation schemes [1,2]. In literature, some examples can be found where both cascoding and cascading with feedforward compensation can be found (e.g., [1]). We present here an alternative feedforward-based gain-boosting technique which integrates efficiently with a folded-cascode amplifier.

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Split compensation for inverter-based two-stage amplifier

Liao

Luo

et al. 2013

Microelectronics Journal

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A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

Cited by 7 publications

References 13 publications

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities

Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities

Folded-cascode amplifier with efficient feedforward gain-boosting

Split compensation for inverter-based two-stage amplifier

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