A 916 nW Power LDO Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

Abstract

This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for RadioFrequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transient-response degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any on-chip and off-chip compensation capacitors. The power is 916 nW. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 μm2. The regulator operates with supply voltages from 1.2V to 2V

Design and Comparison of Constant Transconductance Architectures

“…Furthermore, [15], proposes a new PVT independent constant Gm bias technique applicable to any Iout monotonic convex transconductors. This, [16], method transforms the traditional approach of maintaining a constant transconductance bias into an analog computation procedure. It involves using an input current to calculate the desired constant transconductance bias voltage, denoted as V0.…”