A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator

Zhang, Beichen; Dou, Runjiang; Liu, Liyuan; Wu, Nanjian

doi:10.1109/asscc.2016.7844199

Cited by 8 publications

(3 citation statements)

References 3 publications

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“…However, the gain of passive integrator is very low and the normal operation of dynamic amplifier often requires strict control conditions. So, the robustness and resistance to process parameter drift of the modulator is weak, and ultimately achieve only moderate resolution [11].…”

Section: Introductionmentioning

confidence: 99%

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

Kong

2022

Journal of Sensors

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This article proposed a discrete-time single-loop 3rd order 5-bit Sigma-Delta (ΣΔ) modulator for the audio applications. In this modulator, a feed forward path is used to relax the design requirement of amplifier, which can reduce integrator’s output swing. And a 5-bit asynchronous SAR ADC combined with analog summing is adopted to quantify the summation of feedforward signal and loop filter output, which can significantly reduce power consumption. In addition, chopper stabilization technique is used to alleviate the flicker noise introduced by the first integrator. To eliminate the nonlinearity introduced by multibit quantizer, an improved data weighted average algorithm calibration circuit is proposed. The proposed modulator is implemented in 130 nm technology with a 1.12 mm2 core area. Operating at a 2.56MS/s sampling rate, post layout simulation results show that the modulator realizes 121.2-dB SNDR and 125.1-dB DR in a 20 kHz signal bandwidth, it dissipating 516 μW from 1.5 V supply. It also achieves the energy efficiency, as demonstrated by a Schreier figure of merit (FoMS) of 197 dB.

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Section: Introductionmentioning

confidence: 99%

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

Kong

2022

Journal of Sensors

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“…In addition, since the CDAC capacitance tends to be large, driving the sampling capacitance also becomes challenging. A discrete-time (DT) ADC utilizing a dynamic amplifier is another candidate thanks to its simple structure without requiring complex calibration [7], [8]. However, using the dynamic amplifier in the loop has its drawbacks; Its moderate DC gain can not sufficiently suppress the thermal and 1/f noise contributions of the latter stages, which leads to the SNR degradation [7].…”

Section: Introductionmentioning

confidence: 99%

Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers

Matsuoka

Nezuka²,

Iizuka

2022

IEEE Trans. Circuits Syst. II

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This brief proposes a fully dynamic discrete-time ADC using closed-loop two-stage cascoded floating inverter amplifiers (FIA). The proposed FIA uses a non-cascoded FIA as the 1 st stage and a cascoded one as the 2 nd . By using this arrangement as well as applying metal-insulator-metal (MIM) capacitors for floating reservoir capacitors, it stably achieves high gain even with the input common-mode voltage fluctuation without an additional CMFB nor calibrations. The proposed ADC fabricated in a 65 nm standard CMOS process realizes a fully dynamic operation without calibration and achieves 88.5 dB SNDR, 97.9 dB SFDR with an OSR of 256. It consumes 43.5 μW from a 1V supply at a 10 MHz sampling frequency.

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“…Besides, a DTDSM is immune to clock-jitter and can also be operated over a wide range of sampling frequencies [1]. Moreover, since an SC circuit works on the final settled voltage at the end of each clock phase, dynamic amplifiers can be used to realize the loop filter, resulting in power-efficient implementations [2] [3]. On the downside, a DTDSM requires a power-hungry input buffer and an anti-alias filter [4].…”

Section: Introductionmentioning

confidence: 99%

A Discrete-Time Delta-Sigma Modulator with Relaxed Driving Requirements And Improved Anti-Aliasing

Kumar

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a switched-capacitor integrator for discrete-time delta-sigma modulators. Compared to the conventional implementations, the proposed switched-capacitor integrator reduces the power consumed by the input buffer that drives the delta-sigma modulator, by a factor of two. The proposed integrator samples the input in two non-overlapping phases instead of sampling it in a single phase. This way, the input capacitance can be equally distributed among the two phases, resulting in a 2× reduction in the switched capacitor load that needs to be driven by the input buffer. We further show that doing this also introduces notches in the signal-transferfunction of the modulator at odd-multiples of the sampling frequency, thereby preventing aliasing from those frequencies. The proposed integrator is used to design a fourth-order DTDSM in a 180 nm CMOS process. Simulation results show that the modulator achieves a peak signal-to-noise ratio (SNR) of 97.9 dB while consuming 0.86 mW of power.

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A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator

Cited by 8 publications

References 3 publications

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers

A Discrete-Time Delta-Sigma Modulator with Relaxed Driving Requirements And Improved Anti-Aliasing

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