2008
DOI: 10.1109/isscc.2008.4523142
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A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s

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Cited by 22 publications
(14 citation statements)
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“…Some commercial implementations of VD at 10 Gb/s with 4, 8, and 16 states are available in 90 nm CMOS technology [31][32][33]. It should be possible to implement VD's with 64 or 128 states by using the available 28 nm technology.…”
Section: Endnotesmentioning
confidence: 99%
“…Some commercial implementations of VD at 10 Gb/s with 4, 8, and 16 states are available in 90 nm CMOS technology [31][32][33]. It should be possible to implement VD's with 64 or 128 states by using the available 28 nm technology.…”
Section: Endnotesmentioning
confidence: 99%
“…Also sometimes a variable gain amplifier is used to adjust signal swing. This adjustment of signal swing would properly drive ADC [6].…”
Section: Analog and Mixed-mode Frontendmentioning
confidence: 99%
“…1/T, the design can be relaxed by providing MT seconds for the conversion process of the samples. One of the key challenges in the design of such time-interleaved ADCs is maintaining constant gain and sampling phase across the branches, and as a result, considerable calibration and processing circuitry is employed in such architectures [2]. However, once again, the focus of such extended efforts in calibration are not on minimizing the BER of the communication link, but rather in maximizing the signal to noise plus distortion ratio (SNDR) or in minimizing the total harmonic ͬ d͕Ɖ;ƚͿ ďŶ…”
Section: B Sampling-phase Optimized Ber-aware Adc Architecturesmentioning
confidence: 99%