A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range

Peluso, V.; Vancorenland, P.; Marques, A.; Steyaert, Michiel; Sansen, Willy

doi:10.1109/4.735528

Cited by 188 publications

(74 citation statements)

References 15 publications

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“…The extra switched capacitor C DC adds its contribution to the thermal noise [195]. When its value is C S /2, the increase in noise level is 1.8 dB, which can be compensated for by increasing the sampling capacitor by 50%.…”

Section: Power Supply Rejection and Noisementioning

confidence: 99%

“…In an integrator forward biasing the diodes at opamp input during the sampling phase is not easily avoidable (it can, however, be done with yet another set of switched capacitors [196]), and thus the levels are normally different [195]. Figure 10.5 (b) shows again the voltages in the input, the output, and the virtual ground in an SO amplifier.…”

Section: Preventing Charge Leakage From Virtual Groundmentioning

confidence: 99%

“…A switchable opamp ( Figure 10.11) based on class AB operation was proposed in [199] and later utilized in a ∆Σ modulator [195]. The fully differential circuit can operate with a V T + 2V dsat supply and the class AB structure provides a moderate DC gain and high output driving capability.…”

Section: Class Ab Switchable Opampmentioning

confidence: 99%

“…Reduced swing input signal in conjunction with a series switch was used in the ∆Σ modulators presented in [194] and [195]. This is not a true low-voltage technique either, since when the supply voltage is reduced to a level where all switches are still operational the available input signal swing is zero.…”

Section: Input Interfaces For So Circuitsmentioning

confidence: 99%

“…Reported SO circuits include filters [36,193], ∆Σ modulators [194,195], and the author's two pipelined ADCs [8,2].…”

Section: Operation Principlementioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Power Supply Rejection and Noisementioning

confidence: 99%

Section: Preventing Charge Leakage From Virtual Groundmentioning

confidence: 99%