A 9.95 to 11.1Gb/s XFP transceiver in 0.13/spl mu/m CMOS

Kenney, J.G.; Dalton, D.; Eskiyerli, M.H.; Evans, Eric; Hilton, B.; Hitchcox, D.; Kwok, T.; Mulcahy, Daniel M.; McQuilkin, C.; Reddy, V.; Selvanayagam, S.; Shepherd, Paul; Titus, W.; DeVito, L.

doi:10.1109/isscc.2006.1696127

Cited by 3 publications

(5 citation statements)

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“…A classical CDR is implemented using a Type-2 phaselocked loop (PLL) wherein a passive lead-lag analog loop filter is used to set the loop response. Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter [1,2]. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs [3][4][5].…”

mentioning

confidence: 99%

A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery

Yin¹,

Inti²,

Elshazly³

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phaselocked loop (PLL) wherein a passive lead-lag analog loop filter is used to set the loop response. Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter [1,2]. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs [3][4][5].A bang-bang phase detector provides a simple interface to the DLF without any inherent static phase offset (SPO) [1,3]. However, it introduces a large phase quantization error that limits the jitter transfer bandwidth, and its nonlinear behavior makes loop dynamics difficult to control. A time-to-digital converter (TDC) that is realized using a linear phase detector followed by an ADC could provide fixed gain that enables well-controlled loop dynamics and achieve the desired jitter transfer bandwidth [4,5]. However, it is susceptible to ADC nonidealities that manifest as large SPO, as well as additional power for the ADC. In this paper, the advantages of bang-bang and linear phase detectors are combined in a digital CDR to achieve error-free operation and fixed jitter transfer bandwidth, independent of input jitter amplitude. The CDR decouples the tradeoff between jitter generation and jitter transfer by eliminating the phase quantization error in the proportional path, which allows wide loop bandwidth to suppress DCO phase noise and frequency quantization error. Figure 25.3.1 illustrates the proposed CDR architecture. It consists of a frequency-locking loop (FLL) and a Type-2 digital PLL. At start-up, the FLL drives the DCO frequency to within 500ppm of any incoming data rate in a 0.5 to 3.2Gb/s range. The PLL consisting of a linear proportional path and a bang-bang digital integral path achieves frequency and phase lock. A bang-bang Alexander detector recovers the data without any systematic SPO and generates the early/late information to drive the accumulator in the digital integral path. A decimator allows lower clock frequency operation of the digital circuitry.The PLL proportional path is implemented by directly controlling the DCO with a linear Hogge detector, thus eliminating the non-linearity and quantization error of a bang-bang detector [3] and the need for a high resolution TDC [4,5]. Because, only a 3-level DAC is needed to interface Hogge detector outputs to the oscillator, the circuit realization of the proportional path incurs minimal area and power penalty. The infinite DC gain of the digital accumulator forces the bangbang PD to its metastability point and locks the recovered clock (RCK) to the incoming data without any static phase offset. As a result, any offset in the Hogge detector causes periodic modulation at the data rate and introduces a fixed frequency offset and ripple in the pro...

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mentioning

confidence: 99%

A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery

Yin¹,

Inti²,

Elshazly³

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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“…Distinct 20 and 40 dB/dec noise slopes about 1 MHz reflect the summing of 30 dB/dec 1/f noise in the tank and that noise filtered by the ALC before injection into the VCO current source. An integration of this noise over the 50kHz to 80 MHz Sonet OC-192 BW determines the VCO contribution to the overall CDR random JGEN of 3.59mUIrms, ½ the 7mUIrms XFP specification [2]. A compromise between VCO phase noise and pushing can be seen in the measured random (Rj is phase noise dominated) plus periodic (Pj is 3% supply noise dominated) JGEN of the CDR shown in Fig.…”

Section: Measured Resultsmentioning

confidence: 99%

“…The authors thank L. Weida, T. Manning , B. Bombara, and J. Husisian for measurements, D. Casey and D. Potter for chip layout and the authors of [2], the XFP design team.…”

Section: Acknowledgementmentioning

confidence: 99%

“…An overall ratio between ω JTOL and ω JTRAN of 6 is achieved at 2.5 Gb/s in [1], relaxing its VCO's K VCO variation (∆K VCO ) requirements as one result. For some higher data rate systems in small form factors such as the 10Gb/s XFP module, it is desirable to reduce DC power consumption by limiting psh gain, reducing the ω JTOL / ω JTRAN ratio and accepting a tighter specification on ∆K VCO [2]. A goal of ∆K VCO <1.5:1 is desired in [2] and this is set at startup and is in effect as long as the system operates, with no option to trim K VCO by switching in/out varactors to account for voltage or temperature variations.…”

Section: Introductionmentioning

confidence: 99%

“…For some higher data rate systems in small form factors such as the 10Gb/s XFP module, it is desirable to reduce DC power consumption by limiting psh gain, reducing the ω JTOL / ω JTRAN ratio and accepting a tighter specification on ∆K VCO [2]. A goal of ∆K VCO <1.5:1 is desired in [2] and this is set at startup and is in effect as long as the system operates, with no option to trim K VCO by switching in/out varactors to account for voltage or temperature variations. A second order PLL would desire even tighter ∆K VCO since it lacks any separation of ω JTOL and ω JTRAN .…”

Section: Introductionmentioning

confidence: 99%

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10 GHz VCO for 0.13~m CMOS Sonet CDR

Titus

Kenney

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006

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A 10 GHz VCO with 1.3:1 K VCO variation and 2 MHz/V supply pushing is developed for a dual channel Sonet CDR IC using MOS inversion mode varactors with their backgates tied to a common mode voltage and with an automatic leveling loop to control oscillator amplitude and varactor linearization. Three such oscillators are combined with buffers and a passive switch MUX to achieve an 8-12 GHz tuning range and 27mW DC power consumption on a 1.8V unregulated supply. The VCOs are fabricated in a 0.13um CMOS digital process with added MIMCAP support but thin metal interconnect using thick oxide transistors normally provided for 3V I/O. A moderate -112 dBc/Hz phase noise at 1 MHz offset is achieved which is sufficient to exceed OC-192 Sonet random jitter generation requirements by a factor of 2.

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