A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator

Kim, Young‐Ju; Chung, Sang-Hye; Ha, Kwang Soon; Bae, Seung-Jun; Kim, Lee-Sup

doi:10.1109/tcsi.2015.2459557

Cited by 4 publications

(1 citation statement)

References 12 publications

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“…To cover the wide range of data rates of the clock and data recovery (CDR) loops and to compensate for the process, voltage, and temperature (PVT) variations of clock frequency from voltage controlled oscillator (VCO), various frequency acquisition techniques have been utilized [1][2][3][4][5][6][7][8][9] in the serial data interfaces. However, most of these techniques originate from the thought that the phase detectors cannot detect the frequency difference between the received data and the recovered clock in the CDR loops.…”

Section: Introductionmentioning

confidence: 99%

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

Byun¹

2018

Electronics

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Abstract:The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (f DATA ) and the recovered clock frequency (f CLK ) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of f DATA and f CLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.

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Section: Introductionmentioning

confidence: 99%

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

Byun¹

2018

Electronics

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A 0.36 pJ/bit, 0.025 mm<inline-formula> <tex-math notation="LaTeX">${}^{\text{2}}$</tex-math> </inline-formula>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

Bae

Jeong

Park

et al. 2016

IEEE Trans. Circuits Syst. I

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A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector

Byun

2016

IEEE Trans. Circuits Syst. I

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A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator

Cited by 4 publications

References 12 publications

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

More Discussions on Intrinsic Frequency Detection Capability of Full-Rate Linear Phase Detector in Clock and Data Recovery

A 0.36 pJ/bit, 0.025 mm<inline-formula> <tex-math notation="LaTeX">${}^{\text{2}}$</tex-math> </inline-formula>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology

A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector

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