A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter

Sub-sampling PLL techniques

“…Digital background calibration can then be applied to linearize it. An alternative is adding a delta-sigma modulated digital-totime-converter (DTC) to the reference clock path [17][18][19]. This effectively adds a frac-N multiplier before the SSPD/CP so that the sampling point would still be around zero crossings, as if it is still in int-N mode.…”

“…The PD and CP noise is shown to be not multiplied by N 2 , and greatly attenuated by the high phase detection gain, leading to lower in-band phase noise and better PLL FOM. This article reviews the development of the sub-sampling PLL techniques and their applications in recent PLL architectures [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. Section II discusses the classical charge pump PLL.…”

Fractional spur suppression in all-digital phase-locked loops

“…In [10], the spur cancellation is also based on correlation, but it is gradient-based and can reduce the spur level by more than 20 dB. Even for an analog PLL [11], correlation can still be used to adjust the DTC gain. In the following, spurs in the DTC-based ADPLL will be described.…”

Digital-to-Time Converters for spur correction in Digital Frequency Synthesis

“…The delay element is an inverter, followed by a digitally-programmable capacitive load. The DTC is meant to be used inside a sub-sampling PLL [59,60], where only falling edges (turning the sampling switch off) are relevant for the system operation. Therefore, only the DTC falling edges have been optimized for low noise.…”

“…Time or clock generation with high fidelity is at the heart of numerous electronic systems. The rapid development in Time-to-Digital Converters (TDCs) and Digital-to-Time Converters (DTCs) [62], that are increasingly used in Phase-Locked Loops (PLLs) [60,63,64], pushes the required time resolution to well below 1 ps. This chapter targets the measurement of such small timing steps.…”