A 800Mb/s/pin 2Gb DDR2 SDRAM using an 80nm triple metal technology

Kyung, Kye Hyun; Kim, Chi Wook; Lee, Jae Young; Kook, Jeong Hoon; Seo, Sang Soo; Kim, Du Yeul; Kim, Jun Hyung; Jung, Sunghwan; Lee, Hi Choon; Kim, Chul Soo; Jeong, Byung Hoon; Sohn, Young Soo; Hong, Sang Pyo; Lee, Jae Hyung; Yoo, Junghyun; Cho, Soo In

doi:10.1109/isscc.2005.1494072

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

DOI: 10.1109/isscc.2005.1494072

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A 800Mb/s/pin 2Gb DDR2 SDRAM using an 80nm triple metal technology

Kye Hyun Kyung

Chi Wook Kim

Jae Young Lee

et al.

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Cited by 2 publications

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A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

Jeong¹,

Lee²,

Lee³

et al. 2009

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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With the advent of high-performance multi-processing demands for real-time multimedia and broadband networking in battery-based mobile systems, highspeed and low power mobile SDRAM/DDRs are becoming increasingly important. We present an on-the-fly power-cut scheme that can be applied to mobile DRAM without any special modes and a global data-line repeater scheme to reduce the data-line delay. In addition, 4b data prefetch and a ZQ calibrated output driver scheme are used to achieve 4.3GB/s/chip (1066Mb/s/pin) bandwidth with 110mW power dissipation.

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A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

Jeong¹,

Lee²,

Lee³

et al. 2009

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

View full text Add to dashboard Cite

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Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers

Shahab

Zhu

Margaritov

et al. 2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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The slowdown in technology scaling mandates rethinking of conventional CPU architectures in a quest for higher performance and new capabilities. This work takes a step in this direction by questioning the value of on-chip shared lastlevel caches (LLCs) in server processors and argues for a better alternative. Shared LLCs have a number of limitations, including on-chip area constraints that limit storage capacity, long planar interconnect spans that increase access latency, and contention for the shared cache capacity that hurts performance under workload colocation. To overcome these limitations, we propose a Die-Stacked Private LLC Organization (SILO), which combines conventional on-chip private L1 (and optionally, L2) caches with a per-core private LLC in die-stacked DRAM. By stacking LLC slices directly above each core, SILO avoids long planar wire spans. The use of private caches inherently avoids inter-core cache contention. Last but not the least, engineering the DRAM for latency affords low access delays while still providing over 100MB of capacity per core in today's technology. Evaluation results show that SILO outperforms state-of-the-art conventional cache architectures on a range of scale-out and traditional workloads while delivering strong performance isolation under colocation.

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A 800Mb/s/pin 2Gb DDR2 SDRAM using an 80nm triple metal technology

Cited by 2 publications

References 3 publications

A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application

Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers

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