A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips

Su, Jian‐Wei; Chou, Yen-Chi; Liu, Ruhui; Liu, Chun‐Jen; Lu, Pei-Jung; Wu, Ping-Chun; Chung, Yen-Lin; Hong, Li-Yang; Ren, Jin-Sheng; Pan, Tianlong; Jhang, Chuan-Jia; Huang, Wei-Hsing; Chien, Chih-Han; Mei, Peng-I; Li, Sih-Han; Sheu, Shyh-Shyuan; Chang, Shih-Chieh; Lo, Wei‐Chung; Wu, Chih-I; Si, Xin; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Chang, Meng‐Fan

doi:10.1109/jssc.2022.3199077

Cited by 20 publications

(9 citation statements)

References 41 publications

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“…Reference [7] details the specifics of [5]. For the architecture in [7], the storage array lacks the shift function.…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…Reference [7] details the specifics of [5]. For the architecture in [7], the storage array lacks the shift function. Data can only be read out, shifted, and then rewritten to the storage array to complete alignment.…”

Section: Comparison and Discussionmentioning

confidence: 99%

“…In contrast, the approach in this work requires only 0.12 fW for carrying out the same shifting operation. Compared to [7], this work achieves approximately a 6.24× reduction in power consumption during shift operations.…”

Section: Implementation Of In Situ Update and Shift Functionmentioning

confidence: 98%

“…Table 1 compares the energy consumption between the proposed architecture and the architecture in [7] by shifting '11110000' to the right by four bits to obtain '00001111'. The operation in [7] was simulated under the 130-nm process node, with a power consumption of 0.66 fW for reading and rewriting eight-bit data and 0.089 fW for shifting. In contrast, the approach in this work requires only 0.12 fW for carrying out the same shifting operation.…”

Section: Implementation Of In Situ Update and Shift Functionmentioning

confidence: 99%

“…Furthermore, in [7], data-shifting operations can only be done row by row, while the architecture proposed in this work supports parallel shifting operations across multiple rows.…”

Section: Implementation Of In Situ Update and Shift Functionmentioning

confidence: 99%

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A reconfigurable in‐memory‐computation architecture with in‐situ update and shift capability

Liu,

Wang,

Liu

et al. 2024

Electronics Letters

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This work proposes a storage element (SE) design for in‐memory computing (IMC). Using the proposed SE design, an IMC array has been constructed to enable in‐situ updates of stored weights. Compared with some existing related works which employ 2n bit cells for storing an n‐bit value, the proposed structure in this work exhibits a O(n) complexity of area overhead, which means that only n bit cells are needed to store n‐bit values, offering a significant improvement in silicon area usage. Compared to the purely digitally‐controlled weight update schemes, the approach proposed in this work demonstrates an approximate 1.47× increase in power consumption. Furthermore, it exhibits superior robustness compared to existing work. Additionally, the proposed SE design can achieve the necessary shift functionality in the cutting‐edge floating‐point (FP)‐IMC architecture through simple control mechanisms.

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“…Reference [7] details the specifics of [5]. For the architecture in [7], the storage array lacks the shift function.…”

Section: Comparison and Discussionmentioning

confidence: 99%

Section: Comparison and Discussionmentioning

confidence: 99%

Section: Implementation Of In Situ Update and Shift Functionmentioning

confidence: 98%

Section: Implementation Of In Situ Update and Shift Functionmentioning

confidence: 99%

“…Furthermore, in [7], data-shifting operations can only be done row by row, while the architecture proposed in this work supports parallel shifting operations across multiple rows.…”

Section: Implementation Of In Situ Update and Shift Functionmentioning

confidence: 99%

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