A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS

Ma, Shunli; Sheng, Jili; Li, Ning; Ren, Junyan

doi:10.1109/asscc.2017.8240281

Cited by 8 publications

(3 citation statements)

References 2 publications

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“…where 𝑇 𝑚 is the modulation time of the chirp signal and Δ𝑇 is the time interval of the frequency step Δ𝐹. While the prior works provide the range of 𝑓 𝐵𝑊 as in (6), there must exist an optimal loop bandwidth in this interval to achieve the best chirp linearity and this is studied in this article.…”

Section: Pll Dynamic Response Under a Unit Frequency Stepmentioning

confidence: 99%

“…where 𝐵𝑊 𝑐ℎ𝑖𝑟 𝑝 is the chirp bandwidth and 𝛿 𝑓 is the rms FM error. The prior works for improving the range resolution have mostly focused on increasing the chirp bandwidth with less attention on chirp linearity [6][7][8][9][10]. From (1), as the detection range R increases, the impact of chirp nonlinearity on range resolution becomes increasingly important.…”

Section: Introductionmentioning

confidence: 99%

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A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

Zhang,

Lu,

et al. 2024

IEICE Electron. Express

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This article presents a high-linear phase-locked-loop-based (PLL-based) frequency-modulated continuous-wave (FMCW) frequency synthesizer for 77 GHz automotive radar applications. A behavioral model of the rms FM error by constructing the PLL transient response under a unit frequency step and taking into account the slope of the chirp signal is developed. Simulation results demonstrate the effectiveness of the proposed model in optimizing chirp linearity. The behavioral model is used to facilitate the design of the 77 GHz FMCW synthesizer fabricated in a 55 nm CMOS process. A gain linearized varactor approach is also developed to linearize the voltage-controlled oscillator (VCO) gain (𝐾 𝑉𝐶𝑂 ) to ensure constant PLL bandwidth maintaining optimum chirp linearity. Measurement results show that the synthesizer achieves a 1.2 GHz chirp bandwidth, a minimum rms FM error of 42 kHz (0.0035% of the chirp bandwidth) under a 4.219 MHz/𝜇s chirp slope while consuming 74.6 mW of power. The measured integer-N mode and fractional-N mode phase noises normalized to 78 GHz are -81.6 dBc/Hz and -80.1 dBc/Hz at 1 MHz offset, respectively.

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Section: Pll Dynamic Response Under a Unit Frequency Stepmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

Zhang,

Lu,

et al. 2024

IEICE Electron. Express

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show abstract

“…Accordingly, sub-centimeter azimuthal and range resolution needs more than 100GHz carrier frequency and more than 10GHz modulation bandwidth in order to obtain better 3-D image pixels. A 31.5GHz FMCW with a bandwidth of 7 GHz has been reported to achieve 2-cm resolution for fine movement of gesture [2]. Recently released is the 10-40GHz wide-band FMCW radar system for detecting concealed weapons and liquid bombs in thick clothes and shoes at security check [3], which is implemented using SiGe device.…”

Section: Introductionmentioning

confidence: 99%

A Ka-Band FMCW PLL Synthesizer with 8.5-GHz Bandwidth for High-Precision High-Resolution Sub-mmWave Radar Sensing

Lee

Baek

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 31.4-39.9GHz mmWave PLL synthesizer for FMCW radar applications is proposed that consists of a complementary Colpitts-assisted class-B/C VCO, a programmable quadratic-curved charge pump, and a digital chirp-code generator. The complementary Colpitts oscillator is employed to supply more negative resistance around 40GHz. The charge pump produces quadratic-curved current to keep loop bandwidth constant. The fractional-N PLL synthesizer achieves locking range of 31.4-39.9GHz, a minimum FM rms error of 160 kHz, a high-speed chirp rate of 50s, and a maximum FM modulation bandwidth of 8.5 GHz. The PLL implemented by using 65nm CMOS process accomplishes phase noise of -89dBc/Hz at 1MHz offset from 33.9GHz and consumes 60mW.

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Transformer-Based Ultra-Wide Band 43 GHz VCO in 28 nm CMOS for FMCW Radar System

Chen

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS

Cited by 8 publications

References 2 publications

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

A Ka-Band FMCW PLL Synthesizer with 8.5-GHz Bandwidth for High-Precision High-Resolution Sub-mmWave Radar Sensing

Transformer-Based Ultra-Wide Band 43 GHz VCO in 28 nm CMOS for FMCW Radar System

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