A 79-GHz Adaptive-Gain and Low-Noise UWB Radar Receiver Front-End in 65-nm CMOS

Jang, Jaeduck; Oh, Juntaek; Kim, Choul‐Young; Hong, Songcheol

doi:10.1109/tmtt.2016.2523511

Cited by 21 publications

(17 citation statements)

References 19 publications

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“…The receive path consists of a low noise amplifier with adaptive gain control above 20 dB, g m ‐boosted sub‐harmonic mixers, variable gain amplifiers, a Wilkinson divider, and a broadside 45° coupler. The receiver has a maximum conversion gain of 52 dB and a noise figure of ∼13 dB in the range of 0.01–3.75 GHz at each I / Q path in the simulation; these are similar to the results described by Jang et al…”

Section: System and Circuit Designsupporting

confidence: 86%

“…The receive path consists of a low noise amplifier with adaptive gain control above 20 dB, g m -boosted sub-harmonic mixers, variable gain amplifiers, a Wilkinson divider, and a broadside 458 coupler. The receiver has a maximum conversion gain of 52 dB and a noise figure of $13 dB in the range of 0.01-3.75 GHz at each I/Q path in the simulation; these are similar to the results described by Jang et al 6 Figure 1B shows the radar transceiver chip realized with a 65-nm RF CMOS process. It has an area of 2.4 mm 2 , including bonding pads, and consumes 368 mW with supply voltages of 1.2, 1.5, and 2 V for individual block testing, as shown in Figure 2.…”

Section: S Y S T E M a N D C I R C U I T De S I G Nsupporting

confidence: 82%

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A fully integrated W‐band pulse compression radar CMOS transceiver

Kim

Jang

Hong

2017

Micro & Optical Tech Letters

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A fully integrated ultra‐wideband (UWB) W‐band pulse compression radar transceiver in a 65‐nm CMOS technology is presented. The transceiver adopts a pulse compression scheme for high power spectral density with low TX leakage. Two identical voltage controlled oscillators, which are coupled through the second harmonic, are designed to achieve high output power and low phase noise without buffers. A transformer‐based local oscillator distribution network is proposed to achieve both small chip area and high port‐to‐port isolation. The transceiver chip produces 7.5‐GHz UWB RF pulses with 14.5‐dBm peak output power in the tuning range of 75–81 GHz, while the receiver shows a dynamic range of above 60 dB. The radar module was realized with waveguide transitions from a micro‐strip to a WR‐10 waveguide, and was capable of differentiating two targets with 6.5‐cm separation within 30 m distance.

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Section: System and Circuit Designsupporting

confidence: 86%

Section: S Y S T E M a N D C I R C U I T De S I G Nsupporting

confidence: 82%

A fully integrated W‐band pulse compression radar CMOS transceiver

Kim

Jang

Hong

2017

Micro & Optical Tech Letters

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“…For the better performance of radar receiver, LNA should have a noise figure of less than 5dB [4]. The simulation result of noise figure of the proposed LNA has attained 0.9dB, as illustrated in Fig.…”

Section: B S-parametersmentioning

confidence: 94%

“…A Two Stage DifferentialCascode LNA with an ADB circuit in the second stage is suitable for automotiveradar applications in 77-80 GHz range [4]. The CMOS circuit used in radars gets saturated when input power is high and leads to incorrect range of the object to be detected.…”

Section: Proposed Low Noise Amplifier With Adaptive Biasingmentioning

confidence: 99%

“…This is common phenomena observed in high frequencies of gigahertz range. To solve the problem of saturation a principle of adaptive biasing is introduced in the second stage of LNA [4]. However, there are couple of problems associated with it like overall gain range is reduced, power consumption is increased and large area is needed to constitute two differential stages and two ADB circuits.…”

Section: Proposed Low Noise Amplifier With Adaptive Biasingmentioning

confidence: 99%

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A 79GHz Adaptive Gain Low Noise Amplifier for Radar Receivers

Manjula¹,

Bevi²

2018

IJET

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This paper presents an Adaptive Gain 79GHz Low Noise Amplifier (LNA) suitable for Radars applications. The circuit schematic is a two stage LNA consists of Differential cascode configuration followed by a simple common source amplifier with an Adaptive Biasing (ADB) circuit. Adaptive biasing is a three-stage common source amplifier to decrease output voltage as input power increases. The circuit is simulated in 180nm CMOS technology and the simulation results have proved that the circuit operates at the center frequency 79GHz with adaptive biasing for adaptive gain. The gain analysis shows a decrease of 35-30dB with an increase in input power -50 to 0 dB. At 79GHz the circuit has achieved the input reflection coefficient (S11) of -24.7dB, reverse isolation (S12) of -3 dB, forward transmission coefficient (S21) of -2.97dB and output reflection coefficient (S22) of -5.62 dB with the reduced noise figure of 0.9 dB and a power consumption of 236 mW.

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A 45- to 64-GHz ultra-low-power and low-LO-power sub-harmonic down-conversion mixer with merged self-biased trans-impedance amplifier in 90-nm CMOS

Chi

Chou

Huang

et al. 2017

Microw. Opt. Technol. Lett.

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A 45‐ to 64‐GHz ultra‐low‐power single‐ended sub‐harmonic down‐conversion mixer with a merged structure fabricated in 90‐nm CMOS process with triple‐well NMOS devices is presented. The mixer core is merged directly with self‐biased trans‐impedance amplifier (TIA) to omit its traditional load stage and to enhance the conversion gain. By using weak‐inversion bias technique in a source‐driven topology, the mixer core only needs quiescent current of μA which can be supported from TIA via the feedback resistor. The sub‐harmonic mixers can work effectively for millimeter wave (MMW) system by employing local oscillator (LO) frequency that is only half of the fundamental mixer. When operating with the optimal low LO power of −3.5 dBm at 30 GHz, the mixer exhibits a maximum conversion gain (CG) of 6.4 dB and 2 LO‐to‐RF isolation higher than 46.5 dB from 45 to 64 GHz. The total power consumption is 1 mW at 0.8 V. The calculated figure of merits (FOM) with the consideration of CG and power consumption is excellent among the reported mixers operating at V‐band in CMOS process.

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A 79-GHz Adaptive-Gain and Low-Noise UWB Radar Receiver Front-End in 65-nm CMOS

Cited by 21 publications

References 19 publications

A fully integrated W‐band pulse compression radar CMOS transceiver

A fully integrated W‐band pulse compression radar CMOS transceiver

A 79GHz Adaptive Gain Low Noise Amplifier for Radar Receivers

A 45- to 64-GHz ultra-low-power and low-LO-power sub-harmonic down-conversion mixer with merged self-biased trans-impedance amplifier in 90-nm CMOS

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