A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS

Teh, Chen Kong; Fujita, Takeshi; Hara, Hiroyuki; Hamada, Mototsugu

doi:10.1109/isscc.2011.5746344

Cited by 63 publications

(46 citation statements)

References 6 publications

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“…Table I shows the transistor comparison of pulsed latches and flip-flops. The transmission gate pulsed latch (TGPL) [7], hybrid latch flip-flop (HLFF) [8], conditional push-pull pulsed latch (CP3L) [9], Power-PC-style flip-flop (PPCFF) [10], Strong-ARM flip-flop (SAFF) [11], data mapping flip-flop (DMFF) [12], conditional precharge sense-amplifier flip-flop (CPSAFF) [13], conditional capture flip-flop (CCFF) [14], adaptive-coupling flip-flop (ACFF) [15] are compared with the SSASPL [6] used in the proposed shift-register. When counting the total number of transistors in pulsed latches and flip-flops, the transistors for generating the differential clock signals and pulsed clock signals are not included because they are shared in all latches and flip-flops.…”

Section: B Chip Implementationmentioning

confidence: 99%

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Low-Power and Area-Efficient Shift Register Using Pulsed Latches

Yang

2015

IEEE Trans. Circuits Syst. I

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This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 CMOS process with . The core area is . The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops.Index Terms-area-efficient, flip-flop, pulsed clock, pulsed latch, shift register.

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Section: B Chip Implementationmentioning

confidence: 99%

“…The SSASPL uses 7 transistors, which is the smallest number of transistors among the pulsed latches [6]- [9]. The PPCFF uses 16 transistors, which is the smallest number of transistors among the flip-flops [10]- [15].…”

Section: B Chip Implementationmentioning

confidence: 99%

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

Yang

2015

IEEE Trans. Circuits Syst. I

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“…As a result, the impact of power reduction can decrease. Circuits as well as preset operation have an equivalent drawback [8].The adaptivecoupling sort FF (ACFF) [9], shown in Fig 4, is predicated on a 6-transistor memory cell. During this circuit, rather than the unremarkably used doublechannel transmission-gate, a singlechannel transmission-gate with further dynamic circuit has been used for the information line so as to scale back clockrelated transistor count.…”

Section: Related Workmentioning

confidence: 99%

Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC

Lakshminarayanan¹,

Jayapal²,

Shankar³

et al. 2014

International Journal of Advanced Research in Computer and Comm

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An extremely low-power flip-flop named topologically-compressed flip-flop is planned. As compared with standard FFs, the FF reduces power dissipation by seventy fifth at 1/3 information activity. This power reduction magnitude relation is that the highest among FFs that are reported thus far. The reduction is achieved by applying topological compression methodology, merger of logically equivalent transistors to associate unconventional latch structure. The terribly little variety of transistors, only three, connected to clock signal reduces the facility drastically, and therefore the smaller total transistor count assures identical cell space as standard FFs. In addition, absolutely static full-swing operation makes the cell tolerant of provide voltage and input slew variation. associate experimental chip design with forty nm CMOS technology shows that nearly all standard FFs are replaceable with planned FF whereas protective the same system performance and layout space.

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“…As an essential component of sequential circuits, flipflops have a large impact on the area, speed and power consumption of modern digital circuits [1]. Flip-flops can be built using either static or dynamic design [2].…”

Section: Introductionmentioning

confidence: 99%

“…Static flip-flops are usually based around two inverter-based latches, that have a large impact on area and delay. However, flip-flops based on dynamic logic have advantages in high operating speed and area density compared to static ones [1]. Most flip-flops require both clock signal and its inversion, which challenges clock tree synthesis.…”

Section: Introductionmentioning

confidence: 99%

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs

Tang

Zhang

Gaillardon

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and highspeed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. As a promising approach to keep the pace of Moore's Law, functionality-enhanced devices with multiple independent gates have drown many recent interests. In particular, Three-Independent-Gate Silicon Nanowire FETs (TIG SiNWFETs) can realize the functionality of two serial transistors in a single device. Therefore, they open new opportunities to compact designs in both arithmetic and control circuits. In this paper, we propose TSPC flip-flop implementation with asynchronous set and reset using the compactness of TIG SiNWFET. Electrical simulations show that TIG SiNWFET-based TSPC flip-flop improves nearly 20%, 30% and 7% in area, delay and leakage power respectively as compared to its LSTP FinFET counterpart at 22nm.

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A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS

Cited by 63 publications

References 6 publications

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs

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