A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist

Brandt, Brian; Lutsky, J.J.

doi:10.1109/4.808903

Cited by 62 publications

(31 citation statements)

References 13 publications

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“…The two quantizers work concurrently, so it is not necessary to wait for the completion of the fine quantization to take the next sample. ADCs using this principle are described in [61,62]. Since performing the conversion in multiple steps using several quantizers reduces the resolution of each of them, and that pipelining allows all the stages to work concurrently, it seems logic to use many pipelined stages each with a low resolution quantizer (see Fig.…”

Section: Multi-step Adc Architectures With Pipelining and Residue Ampmentioning

confidence: 99%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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Section: Multi-step Adc Architectures With Pipelining and Residue Ampmentioning

confidence: 99%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…Few SHAs capable of holding the output for a full clock cycle were proposed in the literature [2][3][4][5][6]. A true SHA samples the analog input signal during a short time and then holds the signal during almost the full clock period giving the analog-to-digital converter about twice the time to perform the conversion similar to track-and-hold amplifier (THA).…”

Section: Introductionmentioning

confidence: 99%

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Harb

2010

Analog Integr Circ Sig Process

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Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 lm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 lV and the error introduced by the rectification with respect to the non rectified signal is less than -100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.

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“…General diagram of Analog-to-Digital Converter (ADC) pipeline 5 bits is shown in Figure 1, and further in references (Lewis et al, 1992;Cho & Gray, 1994;Brandt & Lutsky, 1999).…”

Section: Adc Pipeline and Operational Modementioning

confidence: 99%

Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

Ndiaye¹,

Dzahini²,

Ndiaye³

et al. 2012

APR

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The growing use of digital processing in analog environments underlines the importance of Analog Digital Converter (ADC) occurrence in circuitry. The quality and reliability of the conversion are closely linked to the Sample and Hold (SH) performance. Actually SH is a key component in the Analog/Digital chain. The Operational Amplifier being at the heart of the SH influences its output and subsequently impacts the reliability and quality of the conversion. In this paper we present the impact of both Operational Amplifier intrinsic characteristics and external factors such as injected charges, and clock noise on the SH overall performance. We limit our consideration to the offset and parasite capacities as the only relevant Operational Amplifier intrinsic characteristics. We'll introduce the Operational Amplifier and SH functional characteristics then address the impact of each of these parameters on the SH output which the ADC works on. A behavioral description of the Operational Amplifier based on the Verilog-A language under Cadence approach is used. Furthermore a behavioral/analog mixed description is considered for the SH: the Operational Amplifier described behaviorally in Verilog-A is associated to analog components in Cadence libraries and CMOS switches act as SH. However this simplistic approach doesn't reflect all the challenges involved, because it is not enough to connect a SH to ADC to flawlessly digitalize an analog signal. The SH architecture and the Operational Amplifier characteristics play also a role for a reliable sampling and therefore a good quality conversion prospect.In this study the SH performance is evaluated through its non-linearity which in turn determines the sampling accuracy a key factor for a conversion. This study is as shown that small amplitude signals are more sensible to sampling errors related to Operational Amplifier offset. Furthermore the stray capacities attenuate the SH signal output. The injected charges and the clocknoise as strongly interrelated contribute to the non-linearity of the conversion chain.

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A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist

Cited by 62 publications

References 13 publications

Recent Advances and Trends in High-Performance Embedded Data Converters

Recent Advances and Trends in High-Performance Embedded Data Converters

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance

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