A 73dB-A Audio VCO-ADC Based on a Maximum Length Sequence Generator in 130nm CMOS

Pérez, Carlos; Quintero, Andrés; Amaral, P.; Wiesbauer, A.; Hernández, Luis

doi:10.1109/tcsii.2021.3073085

Cited by 15 publications

(11 citation statements)

References 13 publications

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“…In a more realistic design, V in must be sufficiently attenuated [toward the K tune = 0.1 tuning curve of Fig. 3(a)] so that V tune exercises only a relatively linear portion of the VCO tuning curve [24], [34], [35]. This reduction in K tune comes at the severe cost of both a higher thermal and quantization noise.…”

Section: B Deep-subthreshold Design Challengesmentioning

confidence: 99%

“…3(b)]. Coarse-fine counting FDC architectures [30], [31], [34], [35] can accommodate f VCO f CLK /2 efficiently although, contrarily, they embed edge-triggered sequential logic that must operate at a speed even higher than f CLK (which, as stated earlier, should conveniently be maximized). Moreover, intra-die mismatch induces random propagation delay variability that impacts the reliability of high-speed flip-flops, leading to setup and hold time violations.…”

Section: B Deep-subthreshold Design Challengesmentioning

confidence: 99%

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A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Nguyên

Schembari

Staszewski

2022

IEEE J. Solid-State Circuits

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This article demonstrates the potential of deepsubthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm 2 and consumes 15.9 µW, resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

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Section: B Deep-subthreshold Design Challengesmentioning

confidence: 99%

Section: B Deep-subthreshold Design Challengesmentioning

confidence: 99%

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Nguyên

Schembari

Staszewski

2022

IEEE J. Solid-State Circuits

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“…In fact, the coarse-fine partition brings additional timing issues due to the delay skew between the coarse and fine quantizers, along with phase delay mismatches within the finequantizer itself. Architectures utilizing phase reordering [37], scrambling [38] or linear-state feedback registers [39] can be employed, at the cost of an increased system complexity. It remains to be seen whether such solutions can be efficiently ported to the deep-subthreshold environment without functionally limiting its operation to a very slow, suboptimal clock speed, where constraints such as leakage power, mismatches, variability and exponential decrease in maximal speeds place significant boundaries on what can be practically implemented.…”

Section: B Counter-based Fdcmentioning

confidence: 99%

Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs

Nguyên

Schembari

Staszewski

2023

IEEE Trans. Circuits Syst. I

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A frequency-to-digital converter (FDC) performs the role of precise frequency digitization within a voltagecontrolled oscillator (VCO)-based ADC. To be compatible with energy-harvesting (EH) Internet-of-Things (IoT) devices, the development of ultra-low-voltage (ULV) FDCs is crucial, where the primary focus must be directed towards the maximization of data throughput under dramatic constraints of reliability and timing variability associated with deep-subthreshold operation. This article investigates the speed maximization of a 0.2 V fullcustom ULV FDC design, consisting of an array of several parallel XOR-based FDC units, and the multi-rate decimationfiltering digital back-end. At the core of this broad exploration is a high-speed sense-amplify phase sampler (PS) featuring hardware redundancy, capable of sampling the phase of lowvoltage-swing inputs. Particular focus is placed on the yieldbased reliability-driven design methodology for the sense-amplify phase-sampling circuits running up to 40 MS/s and practical variability-mitigation strategies. To overcome the speed bottleneck in the digital back-end, a fully parallel bitstream-processing architectural composition of the computations for summation and decimation are proposed. Experimental verification through measurements of the FDC integrated within a 10-bit 160 kHz bandwidth (BW) open-loop VCO-based ADC across clock frequency with supply variations demonstrate robust operation of the first 0.2 V multi-phase FDC in the advanced 28 nm CMOS process.

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“…Diverse hybrid structures with VCOs have been published: with VCOs as integrators/quantizers in CTSDMs [19][20][21][22][23], placing it into SAR-based structures for pipeline ADCs [24][25][26][27] or in multi-stage noise shaping (MASH) architectures [28][29][30][31]. If we look for simplicity, they are of special interest if a ring-oscillator is used in an open-loop configuration [32][33][34]. Apart from its simple digital architecture, composed of CMOS logic gates (NOT gates), the spectral properties of pulse frequency modulation enable first-order noise-shaped output data, with a performance similar to CTSDMs [35].…”

Section: Introductionmentioning

confidence: 99%

Ring-Oscillator with Multiple Transconductors for Linear Analog-to-Digital Conversion

et al. 2021

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This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.

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A 73dB-A Audio VCO-ADC Based on a Maximum Length Sequence Generator in 130nm CMOS

Cited by 15 publications

References 13 publications

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs

Ring-Oscillator with Multiple Transconductors for Linear Analog-to-Digital Conversion

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