A 72-fs-Total-Integrated-Jitter Two-Core Fractional-<i>N</i> Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Buccoleri, Francesco; Dartizio, Simone M.; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, A.L.; Levantino, Salvatore

doi:10.1109/jssc.2022.3228899

IEEE J. Solid-State Circuits

2023

DOI: 10.1109/jssc.2022.3228899

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A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Francesco Buccoleri

Simone M. Dartizio

Francesco Tesolin

et al.

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A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

Cited by 2 publications

References 41 publications

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A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

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