A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

Temporiti, Enrico; Albasini, G.; Bietti, I.; Castello, R.; Colombo, M.

doi:10.1109/jssc.2004.831598

Cited by 134 publications

(47 citation statements)

References 8 publications

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“…Furthermore, this solution can be used to make present multistandard synthesizers cover WCDMA band VII, since usually only the LO's for the lower bands are generated. In any case, the power penalty of 6 mW seems definitely reasonable, considering that GSM and GSM/WCDMA synthesizers typically dissipate several tens of milliwatts [14][15][16][17][18][19]. From the perspective of area consumption, the overhead of the proposed multiplier is totally negligible: as a matter of fact, the proposed circuit is based on digital gates and the area consumption will be dominated by the passive components of the loop filter of Fig.…”

Section: Resultsmentioning

confidence: 99%

A local oscillator for WCDMA band VII based on frequency multiplication

Gerosa

Bevilacqua

Neviani

2012

Analog Integr Circ Sig Process

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This work explores the generation of a local oscillator for WCDMA band VII based on frequency multiplication of a GSM reference. The frequency multiplier is based on a PLL, which includes a compact VCO based on a ring oscillator. A proper PLL design allows to sufficiently reject the relative high VCO phase noise, complying with the WCDMA requirements. The effectiveness of the proposed approach is proved with the design of the whole multiplier in a 90 nm CMOS technology. The generated oscillation ranges from 3 to 6 GHz, while the simulated phase noise is −120 and −144 dBc/Hz at a frequency offset of 0.6 and 20 MHz, respectively, dissipating 6.3 mW

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Section: Resultsmentioning

confidence: 99%

A local oscillator for WCDMA band VII based on frequency multiplication

Gerosa

Bevilacqua

Neviani

2012

Analog Integr Circ Sig Process

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“…It is generally studied at a functional design level in Matlab/Simulink software [1] [2] before going down in the hierarchical design flow to achieve a transistor level topology. In fact, the last takes an extremely long simulation runtime and makes very hard the optimization of the modulator topology.…”

Section: Presentation Of the Msk Modulatormentioning

confidence: 99%

“…A key limitation in such systems is that the low-pass filter response of the synthesizer dynamics causes inter-symbol interference in the transmitted data. Techniques have recently emerged that focus on increasing synthesizer bandwidth [1] [2].…”

Section: Introductionmentioning

confidence: 99%

High level optimization of a MSK modulator using Hoke_D4 experimental design

Sahnoun

Fakhfakh

Nouri

et al. 2010

5th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era

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The purpose of this work is to design a MSK modulator capable to work at a high data modulation. To achieve a low simulation runtime, the modulator is described in VHDL-AMS hardware description language. It is optimized by applying the "Hoke_D4 experimental design" with five factors having in view to minimize the modulator response time. An optimum solution is performed with the help of NEMROD software.

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“…As mentioned before, frequency synthesizers are used to produce a stable and precise local oscillator frequency for channel switching and are one of the most important blocks for wireless transceiver. In the wireless transceiver system, the frequency synthesizer lock time should be less than the required time for channel switching according to the wireless standards [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. For voice and data communication, there are many standards which define how devices communicate with each other.…”

Section: Lock Time For Ds-fn-pll Frequency Synthesizermentioning

confidence: 99%