A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit
Wanlong Zhao,
Yuejun Zhang,
Liang Wen
et al.
Abstract:Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of… Show more
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