A 7.5–9 GHz GaAs Two-Channel Multi-Function Chip

Abstract

Based on the 0.5 μm GaAs enhancement/depletion (E/D) Pseudomorphic High Electron Mobility Transistor (pHEMT) process, a 7.5–9 GHz two-channel amplitude phase control multi-function chip (MFC) was developed successfully. The chip was integrated with a 6-bit digital phase shifter, a 6-bit digital attenuator, and a single pole single throw (SPST) switch in each channel. A design for the absorptive SPST switch is deployed to optimize the return loss and control channel array calibration. In the 8 dB and 16 dB attenuation bit, a switched-path-type topology is employed in order to obtain a good flatness of attenuation characteristic and achieve low additive phase shift. A 27-bit serial-to-parallel converter (SPC) was introduced to decrease the control lines and pads of the chip, and the power consumption was less than 70 mW. The measurement result shows that the insertion loss is less than −13 dB and the return loss is better than −19 dB. In both channels, the 64-state root mean square (RMS) errors of the phase shifter is less than 2° and the RMS parasitic amplitude error is less than 0.2 dB. The RMS attenuation error is less than 0.45 dB and the RMS parasitic phase error is less than 2.4°. The size of the chip is 3.5 mm × 4.5 mm.

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

“…Along with the number of bits, the designation of the bits within the core-chip is reported, when available: clearly, most of the bits are used for the phase and amplitude control, while, depending on the chip functionalities, up to six bits [15] are adopted for the switches. It is worth to note than in several cases [16][17][18][19] a serial output bit is also available, allowing to connect more CCs in daisy chain and configure them sequentially, and/or to test/monitor the SIPO output. In principle, it is sufficient to route the last bit to an output pad, possibly after level shifting/buffering as in [17].…”

“…In principle, it is sufficient to route the last bit to an output pad, possibly after level shifting/buffering as in [17]. Even if practically negligible, this represents a slight alteration in the load of the last bit with respect to all other bits, therefore in [18] an extra bit is included to be used specifically for the data output line. In [20] the number of SIPO bits is double than necessary so as to simultaneously load two different control words, containing, respectively, the receive-and transmit-mode CC configuration and stored in the even and off SIPO bits.…”

A Ku-Band GaAs Multifunction Transmitter and Receiver Chipset

“…In recent years, several multifunction chips have been reported in GaAs or silicon technologies [1,[4][5][6][7][8][9][10][11][12][13]. Silicon-based multifunction chips are favorable for their easy integration with digital circuits and low cost in the case of mass chip production [4].…”

“…Therefore, it is more attractive to use GaAs technology for broadband multifunction chips with high gain, high output power and low noise figures. There are several articles which have reported on GaAs multifunction chips [1,[8][9][10][11][12][13]. Nevertheless, many chips integrate only some, and not all, of the essential circuit blocks required for phased arrays, including a phase shifter, attenuator, amplifier and digital control circuit [1,8,9].…”

“…There are several articles which have reported on GaAs multifunction chips [1,[8][9][10][11][12][13]. Nevertheless, many chips integrate only some, and not all, of the essential circuit blocks required for phased arrays, including a phase shifter, attenuator, amplifier and digital control circuit [1,8,9]. Other reports show narrowband operation [8,10] or relatively limited output power and high noise figures [11,13].…”