An energy-efficient DAC scheme with most significant bit (MSB) split structure is proposed for successive approximation register (SAR) ADCs. The proposed scheme consumes no switching energy in the first three conversion cycles, and the switching energy for the rest cycles is further optimised using the single-side switching method. Furthermore, the proposed capacitor-swapping reset scheme eliminates the reset energy. Taking the reset energy into consideration, the proposed scheme reduces the total average energy by 99.23% compared with the conventional SAR ADC architecture and hence achieves high energy-efficiency.