A 6bit, 7mW, 250fJ, 700MS/s subranging ADC

Asada, Yusuke; Yoshihara, Kei; Urano, Tatsuya; Miyahara, Masaya; Matsuzawa, Akira

doi:10.1109/asscc.2009.5357198

Cited by 21 publications

(17 citation statements)

References 13 publications

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“…The output results of the ADC are transferred to digital baseband (DBB) after slowing down its data rate by serialto-parallel (S/P) circuit as the operating frequency of DBB is only 288 MHz. Figure 6 shows a double-tail latched comparator with capacitive offset cancellation for the flash ADCs [7]. The offset voltage of the comparator can be reduced by adjusting the capacitance at the output nodes of the first stage of the double-tail latched comparator.…”

Section: Rtuif12mentioning

confidence: 99%

An 84 mW 0.36 mm<sup>2</sup> analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS

Miyahara

Sakaguchi

Shimasaki

et al. 2012

2012 IEEE Radio Frequency Integrated Circuits Symposium

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This paper presents low-power, small area analog baseband (ABB) circuits for 60 GHz wireless transceiver in 40 nm CMOS. The ABB circuits consist of 0-to-40 dB VGAs and 5-bit 2304 MS/s flash ADCs for the receiver, and 6-bit 3456 MS/s DACs for the transmitter. The VGAs also work as 2-2-1 order low-pass filters by using negative capacitance generator. The receiver demonstrates SNDR of 27.3 dB at 2304 MS/s with 16 dB VGA gain. The DAC demonstrates SFDR of 40 dB at 3456 MS/s up to 200 MHz. VGAs, ADCs and DACs consume 18 mW, 24 mW and 42 mW from a 1.1 V supply, respectively. The entire ABB circuits occupy an area of 0.36 mm 2 .

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Section: Rtuif12mentioning

confidence: 99%

An 84 mW 0.36 mm<sup>2</sup> analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS

Miyahara

Sakaguchi

Shimasaki

et al. 2012

2012 IEEE Radio Frequency Integrated Circuits Symposium

Self Cite

View full text Add to dashboard Cite

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“…The interpolation is done by varying the ratio of the input NMOS pair. However the interpolation suffers from drain current mismatch between the input transistors, which is proportional to the overdrive voltage (Vgs-Vth) [2]. If comparators always operate at the same overdrive voltage condition, which corresponds to coarse comparison, it is sufficient to cancel the mismatch of Vgs-Vth.…”

Section: Circuit Design and Techniquementioning

confidence: 99%

A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS

Danjo

Yoshioka

Isogai

et al. 2012

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test

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A 6b 1GS/s subranging ADC with interpolating technique, which has neither a reference resistor ladder nor redundant comparators is presented. Each comparator operates twice each cycle, during coarse and fine decision, for a conversion based on digitally controlled threshold levels. The threshold levels at these decisions are different, so these are adjusted in foreground calibration. The die area is 0.04mm 2 including on-chip digitally threshold control circuit , and power consumption is 9.9mW. SNDR is 32.8 dB is achieved at 1GS/s.

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“…To realize interpolation, is shifted by to create a pair of input signals for interpolation. Then, a 3 bit sub-ADC (CMP1) using gate-weighted interpolation [20], [24] generates the first set of conversion data that are used to control the switches of the capacitor arrays. With the conversion data, the capacitor arrays behave like a pair of capacitive DACs (CDACs) generating the required and signals for the next pipeline stage.…”

Section: Interpolated Pipeline Architecturementioning

confidence: 99%

“…10 shows the schematic of a 3 bit sub-ADC and its dynamic comparator. To remove the references after the first pipeline stage, gate-weighted interpolation technique [20], [24] is applied in all of the sub-ADCs. This technique is simple to realize in the proposed ADC as the sampling capacitors in the first stage and the residue amplifiers in the following stages readily provide the shifted signals ( in the first stage and and in the following stages) required for the gate-weighted interpolation.…”

Section: F Sub-adcmentioning

confidence: 99%

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Lin

Paik

Lee

et al. 2015

IEEE J. Solid-State Circuits

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This paper presents a 0.55 V, 7 bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, high-speed open-loop dynamic amplifiers with a common-mode detection technique are used as residue amplifiers to increase the ADC's speed, to enhance the robustness against supply voltage scaling, and to realize clockscalable power consumption. To mitigate the absolute gain constraint of the residue amplifiers in a pipeline ADC, the interpolated pipeline architecture is employed to shift the gain requirement from absolute to relative accuracy. To show the new requirements of the residue amplifiers, the effects of gain mismatch and nonlinearity of the dynamic amplifiers are analyzed. The 7 bit prototype ADC fabricated in 90 nm CMOS demonstrates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM of the ADC is 240 fJ/conversion-step.

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A 6bit, 7mW, 250fJ, 700MS/s subranging ADC

Cited by 21 publications

References 13 publications

An 84 mW 0.36 mm<sup>2</sup> analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS

An 84 mW 0.36 mm<sup>2</sup> analog baseband circuits for 60 GHz wireless transceiver in 40 nm CMOS

A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

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