A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC

Donnelly, Kevin; Chan, Yiu-Fai; Ho, J.; Tran, Chanh; Patel, Subhash; Lau, Brian; Kim, Jun; Chau, P.S.; Huang, Ching-Chao; Wei, J.; Yu, Leung; Tarver, R.; Kulkami, R.; Stark, D.; Johnson, M.

doi:10.1109/4.545823

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Cited by 15 publications

(1 citation statement)

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“…As interface frequency goes high, there have been many efforts to enhance the performance of an input receiver, such as power consumption [1], sensitiveness to low input swings [2], logic level converting [3], and ISI noise immunity [4]. However, there has been comparatively little concern about the effect on the valid window by the variations of Input CM level.…”

Section: Introductionmentioning

confidence: 99%

A pseudo-differential CMOS receiver insensitive to input common mode level

Kim

Cho

Byun

2005 IEEE International Symposium on Circuits and Systems

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The composite replica-tail-feedback (CRF) bias is proposed to prevent valid window from reducing due to variations of input common mode (CM) level. The CRF bias is applied to a differential static amplifier and a differential clocked receiver. They are fabricated with 0.1µm CMOS process and the supply voltage is 1.2V. When input CM level changes between 0.5V and 1.0V, the static amplifier features output CM level variations of ±2.3% and propagation delay variations of ±7.5% against each average. Under the same condition, the clocked receiver provides zero setup and 60pS hold, and the alterations of hold are 14pS.

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Section: Introductionmentioning

confidence: 99%

et al. 1998

IEEE J. Solid-State Circuits

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A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC

Cited by 15 publications

References 6 publications

A pseudo-differential CMOS receiver insensitive to input common mode level

A pseudo-differential CMOS receiver insensitive to input common mode level

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