A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator

This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 dBc/Hz. The core area of this edge-injection-based DRCO is only 0.08 mm2.

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A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator

Cited by 2 publications

References 8 publications

A High-Performance Low Complexity All-Digital Fractional Clock Multiplier

A High-Performance Low Complexity All-Digital Fractional Clock Multiplier

A High FoM and Low Phase Noise Edge-Injection-Based Ring Oscillator in 350 nm CMOS for Sub-GHz ADPLL Applications

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