A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

Pilo, H.; Arsovski, Igor; Batson, Kevin; Braceras, G.; Gabric, J.; Houle, R.; Lamphier, S.; Pavlik, Frank; Seferagic, Adnan; Chen, Liang‐Yu; Ko, Shang-Bin; Radens, C.

doi:10.1109/isscc.2011.5746307

Cited by 44 publications

(22 citation statements)

References 2 publications

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“…Due primarily to the scaling challenges of the SRAM transistors, such as random/intrinsic variations, the read/write characteristics of the SRAM bit-cells have been controlled by peripheral circuits: (i) for the read margin: hierarchical or short bit-lines and read-assist circuits [4][5][6][7], and (ii) for the write margin: write-assist circuits [8][9][10]. In using the read-assist circuits, the passgate disturbance can be reduced by decreasing the wordline voltage or the bit-line pre-charge voltage.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

“…In [8][9][10], the lower bit-line pre-charge voltage (generated by a local regulator, n-type device's precharge, or pulse techniques) can suppress cell disturbance. The optimal bit-line voltage is about 70% to 80% of power supply voltage, due mainly to reverse stability limitations.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

“…In [4] and [10], the capacitively boosted bit-line is below ground voltage. The coupling occurs after the bitline voltage reaches ground and is floated.…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

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Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Shin

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-There is a trade-off between read stability and writability under a full-/half-select condition in static random access memory (SRAM). Another trade-off in the minimum operating voltage between the read and write operation also exists. A new peripheral circuit for SRAM arrays, called a variation sensor, is demonstrated here to balance the read/write margins (i.e., to optimize the read/write trade-off) as well as to lower the minimum operation voltage for both read and write operations. A test chip is fabricated using an industrial 45-nm bulk complementary metal oxide semiconductor (CMOS) process to demonstrate the operation of the variation sensor. With the variation sensor, the word-line voltage is optimized to minimize the trade-off between read stability and writability (V WL,OPT = 1.055 V) as well as to lower the minimum operating voltage for the read and write operations simultaneously (V MIN,READ = 0.58 V, V MIN,WRITE = 0.82 V for supply voltage (V DD ) = 1.1 V).

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Section: Measurement Results and Discussionmentioning

confidence: 99%

Section: Measurement Results and Discussionmentioning

confidence: 99%

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Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Shin

2014

JSTS:Journal of Semiconductor Technology and Science

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“…As conventional 6T-based SRAM designs fail to operate at low voltage levels, recent work has developed new bit-cell topologies [2]- [6], new array architectures [7]- [9] and various assist techniques [10]- [16] to enable robust operation at low-voltage levels.…”

Section: Introductionmentioning

confidence: 99%

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Sinangil

Chandrakasan

2014

IEEE J. Solid-State Circuits

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Abstract-This paper presents an application-specific SRAM design targeted towards applications with highly correlated data (e.g. video and imaging applications). A prediction-based reduced bit-line switching activity scheme is proposed to reduce switching activity on the bit-lines based on the proposed bit-cell and array structure. A statistically gated sense-amplifier approach is used to exploit signal statistics on the bit-lines to reduce energy consumption of the sensing network. These techniques provide up to 1.9× lower energy/access when compared to an 8T SRAM. These savings are in addition to the savings that are achieved through voltage scaling and demonstrate the advantages of an application-specific SRAM design.

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“…The low-voltage SRAM has been the focus of much research undertaken [1][2][3][4][5], however, special attention has not been focused on the effectiveness of the low-voltage operation for the energy reduction. The energy saving of SRAM with the low-voltage operation is more difficult than that of the logic circuit.…”

Section: Introductionmentioning

confidence: 99%

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme

Kawasumi¹,

Suzuki²,

Moriwaki³

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

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We found the dynamic-energy increase in SRAM caused by V DD reduction under 0.7V. This is caused by the random variability and the total (dynamic + leakage) energy increase is estimated to be 95% at 0.5V. A Bitline Amplitude Limiter capable of compensating this energy degradation is proposed. This limiter reduces dynamic energy by suppressing excess bitline amplitude. And it reduces leakage automatically even during the operation. The speed penalty for introducing this circuit is estimated to be 7%. And the area penalty is less than 2%. The total energy reduction of 26% has been confirmed with simulations at 0.5V. The circuit has been implemented with 40nm CMOS technology and the energy reduction of 19% is confirmed by measurements.

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A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

Cited by 44 publications

References 2 publications

Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Assistive Circuit for Lowering Minimum Operating Voltage and Balancing Read/Write Margins in an SRAM Array

Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9$\times$ Lower Energy/Access

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme

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