DOI: 10.1109/isscc.1982.1156327
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F. Ware

Abstract: RECENTLY WE completed a set of monolithic floating point processors. The set is implemented in a CMOS on sapphire process with four micron feature sizes. There are three processors in the set: an add/subtract chip, a multiply chip, and a divide chip.The primary design goal for the chip set was maximum scalar (single operation) performance, which was achieved by using combinational data path logic. It was also necessary to perform three-chip partitioning so that each of the fundamentally different floating poi…

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