A 64b floating point processor

Abstract

RECENTLY WE completed a set of monolithic floating point processors. The set is implemented in a CMOS on sapphire process with four micron feature sizes. There are three processors in the set: an add/subtract chip, a multiply chip, and a divide chip.The primary design goal for the chip set was maximum scalar (single operation) performance, which was achieved by using combinational data path logic. It was also necessary to perform three-chip partitioning so that each of the fundamentally different floating point operations could be optimized with its own data path. The chip set has about 20 to 30 times the performance of commercially-available 64b floating-point processors.A second design goal was to maximize the ease-of-use of the chip set. The chip set has the following features: Identical pin assignments (64 pins/chip), simple control requirements, static, single-clock edge operation, TTL compatible inputs and outputs, about 400mW per chip, three 16b, 12MHz data buses, tristate output pins. The chip set handles the 32b and 64b floating point and 32b fixed point data types of a minicomputer*. Operations provided include add, subtract, multiply, divide, data type conversion, and N-bit shifting. Figure 1 shows a photograph of the add/subtract chip. The two operands are loaded into the exponent and fraction registers in two or four clock cycles (for 32 or 64b operations). The exponents are compared, and the fraction with the smaller exponent is right shifted so the fractions are aligned. The fractions are added, and the result is normalized by a right shift (operands have the same sign) or by an N bit left shift (different operand signs). The result exponent is corrected for the post normalization. The result fraction is then rounded to the proper precision, and the exponent checked for overflow or underflow. If either has occurred, the appropriate constants are forced. The result is unloaded in two or four clock cycles. It will be noted that the operand loading and result unloading is performed synchronously with respect to the external system. Propagation through the combinational data path logic is asynchronous, and the necessary time delay is provided by an integral number of system clock cycles. The propagation delay is in the range of 400 to 600ns, depending upon the operation.A photograph of the multiply chip appears in Figure 2. When the operands are loaded, a modified Booth encoding is performed on the multiplier fraction. This reduces the number of full adders required in the combinational array by one half, and reduces the propagation delay of the array by the same factor. When the carry save result of the full adder array settles, it is sign corrected and converted t o carry propagate form. The -*HP1000 Chairman: Peter J. Verhofstadt Fairchild Camera/lnstr. Corp. Santa Clara, CAresult fraction is normalized, and the result exponent (the sum of the operand exponents) is conditionally incremented. The fraction is rounded t o the proper precision, and the exponent checked for overflow or underflow (with th...