A 640×640 Fully Dynamic CMOS Image Sensor for Always-On Object Recognition

Park, Injun; Jo, Woojin; Park, Chanmin; Park, Byungchoul; Cheon, Jimin; Chae, Youngcheol

doi:10.23919/vlsic.2019.8778169

Cited by 6 publications

(5 citation statements)

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Section: Complete Low-noise Low-power Readout Circuit Performancementioning

confidence: 98%

“…With such a simulated input-referred noise DCDS value, one can note that the noise floor is then close to 0.7 e−rms. In fact, the resulting simulated noise performance already indicates that the proposed solutions (with the current readout method based on high-order ISD converters) can compete with most of the low-noise modern developments, and is capable of sub-electron noise detection [9,[23][24][25][26][30][31][32][33] without excessively degrading the target CIS DR (maintaining it instead), by using classical low-Vth Surface-channel SF NMOS pixel devices. Bearing this in mind, the method used in this research work, which is supported on the lessons learned and on the experimental data from the legacy test CIS characterization, reinforces the fact that several of the proposed solutions-namely the low noise amplifier structures, the low noise devices, and the low voltage supply-are indeed a means of reaching the sub-electron noise performance.…”

Section: Complete Low-noise Low-power Readout Circuit Performancementioning

confidence: 98%

“…Instead of being located at the PGA stage, which most of the time is exclusive for this stage, there is also the possibility to obtain extremely High CG (HCG) pixels, not only having extremely low FD capacitance values, but also by enabling inpixel amplification capabilities, known to be a useful means of reaching extreme noise performance, thus enabling photon-counting capabilities. This may occur not only due to the HCG feature, but also due to the combination of the HCG values, in conjunction with the usage of amplifying PMOS devices, or with the usage of Buried-channel NMOS devices as the pixel SF driver, given the low 1/f noise power offered by these devices [22][23][24][25][26]. Nevertheless, none of the previous specific cases will be further discussed in this paper, as they serve only the purpose of proper contextualization.…”

Section: Low-light Low-noise Imaging Backgroundmentioning

confidence: 99%

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Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Freitas

Morgado‐Dias

2021

Electronics

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Modern CMOS imaging devices are present everywhere, in the form of line, area and depth scanners. These image devices can be used in the automotive field, in industrial applications, in the consumer’s market, and in various medical and scientific areas. Particularly in industrial and scientific applications, the low-light noise performance or the high dynamic-range features are often the cases of interest, combined with low power dissipation and high frame rates. In this sense, the noise floor performance and the power consumption are the focus of this work, given that both are interlinked and play a direct role in the remaining sensor features. It is known that thermal and flicker noise sources are the main contributors to the degradation of the sensor performance, concerning the sensor output image noise. This paper presents an indirect way to reduce both the thermal and the flicker noise contributions by using thin-oxide low voltage supply column readout circuits and fast 3rd order incremental sigma-delta converters with noise shaping capabilities (to provide low noise output digital samples—74 μVrms; 0.7 e−rms; at 105 μV/e−), and thus performing correlated double sampling in a short time (19 μs), while dissipating significant low power (346 μW). Throughout the extensive parametric transistor-level simulations, the readout path produced 1.2% non-linearity, with a competitive saturation capacity (6.5 ke−) pixel. In addition, this paper addresses the readout parallelism as the main point of interest, decoupling resolution from the image noise and the frame rate, at virtually any array resolution. The design and simulations were performed with Virtuoso 6.17 tools (Cadence Design Systems, San Jose, CA, USA) using Spectre models from TS18IS Image Sensor 0.18 µm Process Development Kit (Tower Jazz Semiconductor, Migdal Haemek, Israel).

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Section: Complete Low-noise Low-power Readout Circuit Performancementioning

confidence: 98%

Section: Complete Low-noise Low-power Readout Circuit Performancementioning

confidence: 98%

Section: Low-light Low-noise Imaging Backgroundmentioning

confidence: 99%

See 1 more Smart Citation

Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Freitas

Morgado‐Dias

2021

Electronics

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“…On a scale of 100 million, only the power consumption of this ADC structure would be close to 10 W, which limits its application in the CIS of a billion-level area array [ 7 , 8 , 9 , 10 , 11 , 12 ]. In view of the current research progress and existing problems, based on the traditional SS ADC, this paper proposed a high-speed fully differential two-step ADC structure applied to CIS, which can ensure the power consumption and area advantages of the SS ADC [ 13 , 14 ].…”

Section: Introductionmentioning

confidence: 99%

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Guo

Wang

2023

Sensors

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The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

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“…CMOS image sensors are widely used in so-called digital still cameras such as smartphones, compact cameras, and single-lens reflex cameras, as well as in surveillance cameras, industrial applications [1][2][3], object recognition [4][5][6][7][8], ToF sensors for distance measurement [9][10][11], and medical applications [12][13][14]. The performance requirements in these fields are low noise, high speed, wide dynamic range, and high resolution, and various technologies have been reported to improve these performances.…”

Section: Introductionmentioning

confidence: 99%

Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for CMOS Image Sensor

Kato

Morishita

Okubo

et al. 2022

Sensors

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The surveillance cameras we focus on target the volume zone, and area reduction is a top priority. However, by simplifying the ADC comparator, we face a new RUSH current issue, for which we propose a circuit solution. This paper proposes two novel techniques of column-ADC for surveillance cameras to improve low-light characteristics. RUSH current compensation reduces transient current consumption fluctuations during AD conversion and utilizing timing shift ADCs decreases the number of simultaneously operating ADCs. These proposed techniques improve low-light characteristics because they reduce the operating noise of the circuit. In order to support small signal measurement, this paper also proposes a high-accuracy evaluation system that can measure both small optical/electrical signals in low-light circumstances. To demonstrate these proposals, test chips were fabricated using a 55 nm CIS process and their optical/electrical characteristics were measured. As a result, low-light linearity as optical characteristics were reduced by 63% and column interference (RUSH current) as an electrical characteristic was also reduced by 50%. As for the high-accuracy evaluation system, we confirmed that the inter-sample variation of column interference was 0.05 LSB. This ADC achieved a figure-of-merit (FoM) of 0.32 e-·pJ/step, demonstrating its usefulness for other ADC architectures while using a single-slope-based simple configuration.

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A 640×640 Fully Dynamic CMOS Image Sensor for Always-On Object Recognition

Cited by 6 publications

References 0 publications

Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Circuit Techniques to Improve Low-Light Characteristics and High-Accuracy Evaluation System for CMOS Image Sensor

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