A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS

Depaoli, Emanuele; Zhang, Hongyang; Mazzini, Marco; Audoglio, Walter; Rossi, Augusto Andrea; Albasini, G.; Pozzoni, M.; Erba, Simone; Temporiti, Enrico; Mazzanti, Andrea

doi:10.1109/jssc.2018.2873602

Cited by 50 publications

(8 citation statements)

References 17 publications

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“…As the interconnection rate increases from 100 to 400 Gb/s in DCs, PAM-4 direct detection format becomes the standard for DR4 and FR4 modules [88] . A single-channel 53 Gb/s PAM-4 transmission has been achieved within a range of up to 40 km [89] . A 5.02 mW/Gbps low-power PAM-4 transceiver is reported, each channel can transmit up to 64 Gb/s in the short-range (SR) transmission range [90] .…”

Section: Four-level Pulse-amplitude Modulationmentioning

confidence: 99%

Silicon photonic transceivers for application in data centers

Wang

Chai

et al. 2020

J. Semicond.

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Global data traffic is growing rapidly, and the demand for optoelectronic transceivers applied in data centers (DCs) is also increasing correspondingly. In this review, we first briefly introduce the development of optoelectronics transceivers in DCs, as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process. We also summarize the research on the main components in silicon photonic transceivers. In particular, quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts. Some of the solutions for high-speed optical interconnection in DCs are then discussed. Among them, wavelength division multiplexing and four-level pulse-amplitude modulation have been widely studied and applied. At present, the application of coherent optical communication technology has moved from the backbone network, to the metro network, and then to DCs.

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Section: Four-level Pulse-amplitude Modulationmentioning

confidence: 99%

Silicon photonic transceivers for application in data centers

Wang

Chai

et al. 2020

J. Semicond.

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“…Fig. 3 illustrates the main circuit of linear equalizer that is designed in this paper, which includes high frequency gain amplifier (high-pass path) and unit gain amplifier (all-pass path) [26,27]. It can achieve the best effect through adjusting the tail current of the high frequency amplifier and the unit gain amplifier, i.e.…”

Section: Half-rate Dfe With Speculative Tapmentioning

confidence: 99%

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

Zhang

Yang

2020

IEICE Electron. Express

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This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual intersymbol interference. The chip area including pads is about 1.2 mm 2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

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“…Two 56-Gb/s NRZ transceivers and a 64-Gb/s PAM4 transceiver proposed in previous works [6][7][8] can be applied for high-speed die-to-die links. However, their energy efficiency falls between 4 and 6 pJ/bit, which is comparatively low.…”

Section: Introductionmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS

Cited by 50 publications

References 17 publications

Silicon photonic transceivers for application in data centers

Silicon photonic transceivers for application in data centers

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

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