A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET

Wang, Luke; Fu, Yingying; LaCroix, Marc-Andre; Chong, Euhan; Carusone, Anthony Chan

doi:10.1109/jssc.2018.2877172

Cited by 27 publications

(11 citation statements)

References 17 publications

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“…For example, PAM-4 signal typically requires a minimum RLM to be at least 92% in many applications. [40][41][42] For the proposed PAM-4 scheme, the different MW fields are applied here, e.g., Ω M = 8.2Γ , 16.2Γ , 18.2Γ , and 19.3Γ , and then the optical PAM-4 signals are obtained with magnitudes of 10, 40, 70, and 100, respectively as shown in Fig. 3(b).…”

Section: Resultsmentioning

confidence: 99%

Optical PAM-4/PAM-8 generation via dual-Raman process in Rydberg atoms

Song 宋,

Yin 尹,

Ren 任

et al. 2024

Chinese Phys. B

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A scheme of optical four-level pulse amplitude modulation (PAM-4) is proposed based on dual-Raman process in Rydberg atoms. A probe field counter-propagates with a dual-Raman field which drive the ground and the excited states transition, respectively, and the Rydberg transition is driven by a microwave (MW) field. A gain peak appears in the probe transmission and is sensitive to the MW field strength. Optical PAM-4 could be achieved by encoding a MW signal and decoding the magnitude of a probe signal. Simulation results show that the differential nonlinearity and the integral nonlinearity of the proposed scheme could be reduced by 5 times and 6 times, respectively, compared with the previous scheme, and the ratio of level separation mismatch is close to the ideal value 1. Moreover, the scheme is extended to optical PAM-8 signal, which may further improve the spectral efficiency.

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Section: Resultsmentioning

confidence: 99%

Optical PAM-4/PAM-8 generation via dual-Raman process in Rydberg atoms

Song 宋,

Yin 尹,

Ren 任

et al. 2024

Chinese Phys. B

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“…For DFE design simplification, the architecture of direct feedback is adopted, and the semi-interleaved feedback method is proposed to further improve the feedback speed under the condition of satisfying key timing constraints [13]. The sampler threshold adaptive operation is added to meet the requirements of the sampler sensitivity caused by the reduction of the PAM4 eye height [14]. At the same time, the adaptive adjustment of the DFE tap expands the applicable range of the transceiver to the channel [15].…”

Section: Figure 1 Overall Block Diagram Of the Transceivermentioning

confidence: 99%

A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Liu

Wen

et al. 2023

Preprint

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To meet the demand of low bit error rate (BER) and high bandwidth for high-speed links, a reliable 112Gb/s four-level pulse amplitude modulation (PAM4) transceiver design scheme with adaptive threshold voltage and adaptive decision feedback equalizer (DFE) is proposed in this paper. In this scheme, three continuous time linear equalizers (CTLE) at the front end of receiver are used to compensate the high-frequency, mid-frequency and low-frequency signals respectively, and the variable gain amplifier (VGA) and saturation amplifier (SatAmp) are used to scale the signal amplitude. In addition to the three data samplers, four auxiliary samplers are also used for threshold adaptation. The sign-sign least mean squares algorithm uses the offset between the data sampler and the auxiliary sampler at the receiver side to drive the auxiliary reference voltage to converge to the signal constellation level, thus ensuring that the eye diagram of the PAM4 received signal has equal spacing and a constant signal-noise ratio (SNR) for the three eyes in the vertical direction. In addition, the adaptive DFE for PAM4 signaling allows the transceiver to better adapt to the channel and thus achieve better equalizer performance. The simulation results show that the PAM4 transceiver design can compensate up to 25dB of channel loss with an average eye height of 59.6 mv and an average eye width of 0.27 UI at a bit error rate of 10− 12 under the condition of 3 tap Feedforward equalizer (FFE) transmitter.

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“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

Section: Interconnectmentioning

confidence: 99%

“…Recently, a dramatic change has been made to break the ice. An amplitude modulation technique, which is called 4-level pulse-amplitude modulation (PAM-4), has been adopted in the industry ( Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ). With PAM-4, the interconnect can transmit two bits in one-bit period, which doubles the effective bandwidth over NRZ.…”

Section: Interconnectmentioning

confidence: 99%

“…On the other hand, we can also make a bigger change on the architecture. In an analog-to-digital converter (ADC)-based interconnect or digital signal processing (DSP)-based interconnect ( LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 ; 2020 ; Im et al, 2020 ; Yoo et al, 2020 ; Harwood et al, 2007 ; Chen & Yang, 2010 ; Wang et al, 2018 ; Palermo et al, 2018 ), the analog front-end circuits of the receiver are replaced by a high-speed ADC, and a large fraction of the equalization and CDR stuffs are done in the digital domain. With that, an extensive equalization with dense digital logic is enabled.…”

Section: Interconnectmentioning

confidence: 99%

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Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET

Cited by 27 publications

References 17 publications

Optical PAM-4/PAM-8 generation via dual-Raman process in Rydberg atoms

Optical PAM-4/PAM-8 generation via dual-Raman process in Rydberg atoms

A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Today’s computing challenges: opportunities for computer hardware design

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