A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree

Itoh, N.; Naemura, Y.; Makino, Hiroshi; Nakase, Y.; Yoshihara, Takuya; Horiba, Y.

doi:10.1109/4.902765

Cited by 44 publications

(22 citation statements)

References 14 publications

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“…This design was detailed further in [12,32]. A number of RB multipliers have been proposed thereafter based on the same architectural concept [5,6,25]. Among them, an ingenious development came from Lee et al [6].…”

Section: Review Of Existing Rb Multipliersmentioning

confidence: 99%

“…The critical paths dominated by digital multipliers often impose speed limits on the entire design. Therefore, there have been an immense volume of publications and endless research interest in the design of energy efficient digital multipliers at different design abstraction levels [5][6][7][8].Most digital multiplier designs are based on the two's complement arithmetic, which is referred to as normal binary (NB) arithmetic as opposed to the redundant binary (RB) arithmetic studied in this chapter. Fast NB multipliers use modified Booth encoders, and 3-to-2 counters or 4-to-2 compressors in a tree structure for parallel computation [9][10][11].…”

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confidence: 99%

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Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Yang

Chang

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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The state-of-the-art digital signal processing applications play an important role in making the complex real-time algorithms for speech, audio, image processing, video, control and communication systems economically feasible [1][2][3][4]. Multiplication is one of the most commonly used arithmetic operators in these applicationspecific datapaths. Comparing with many other arithmetic operations, multiplication is time consuming and power hungry. The critical paths dominated by digital multipliers often impose speed limits on the entire design. Therefore, there have been an immense volume of publications and endless research interest in the design of energy efficient digital multipliers at different design abstraction levels [5][6][7][8].Most digital multiplier designs are based on the two's complement arithmetic, which is referred to as normal binary (NB) arithmetic as opposed to the redundant binary (RB) arithmetic studied in this chapter. Fast NB multipliers use modified Booth encoders, and 3-to-2 counters or 4-to-2 compressors in a tree structure for parallel computation [9][10][11]. In the last three decades, most speed improvements in this architecture have been achieved via extreme circuit optimization and the use of advanced fabrication technology. The gain resulting from architectural innovation is almost stagnant. It is conjecture that new insight into energy efficient multiplier design is likely to be derived from an alternative arithmetic with a different Y. He ( ) •

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Section: Review Of Existing Rb Multipliersmentioning

confidence: 99%

mentioning

confidence: 99%

Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Yang

Chang

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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“…3 indicating the architecture of the MAC diagram which has been designed in this paper. The design consists of one 4 bit parallel adder based Wallace tree multiplier [19], one 10 bit accumulator register, one control logic/DeMUX block, one 8 bit register. The two 4 bit numbers are multiplied and stored in 8bit registers.…”

Section: Circuit Modules and Overall Architecturementioning

confidence: 99%

Implementation of high speed processor for computing convolution sum for DSP applications

Saha

Kumar

Sharma

2015

Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication

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In this paper, we report on transistor level (ASIC) implementation of high speed processor for the first time, for computing convolution sum (linear and circular) of two sequences. The convolution sum was calculated through the orientation of the sequences into array formation for parallel processing, owing towards high speed architecture design. The architectures were implemented and functionality was verified through spice simulator. The mathematical transformation along with binary coded decimal(BCD) arithmetic have been incorporated for the practical implementation of convolution sum, ensure substantial reduction of propagation delay in comparison with earlier reported architectures. The performance parameters such as propagation delay, dynamic switching power consumption were calculated through spice using 90nm CMOS technology. The propagation delay of the resulting 4-point linear convolution was only ~12.79ns and consumes ~27.56mW power with a layout area of ~9.06mm 2 . Moreover, performance parameters of 4-point circular convolution were ~14.8ns propagation delay with ~37.8mW switching power consumption.

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“…Conventional iterative array schemes with canonic interconnections are presented in [1] and [2], where the critical time of the operation is linearly dependent on the bit-length of both operands. Faster implementations are presented in [3], [4], and [9], using the Wallace tree structure for the addition of partial products, but these schemes produce a non-regular layout. In [5], the ModifiedBooth encoding approach is introduced, leading to the reduction of critical time to the half, compared to bit-parallel array schemes.…”

Section: Introductionmentioning

confidence: 99%

A high-speed radix-4 multiplexer-based array multiplier

Bekiaris

Pekmestzi

Papachristou

2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

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This paper presents a new radix-4 multiplexer-based array multiplier, based on a multiplication scheme shown in a previous work, where 4-to-1 multiplexers are used for the computation of partial products. In the proposed design, the rows of the array are reduced to the half, compared to the initial multiplexer-based scheme, as two bits from both operands are processed at each step. The proposed scheme is compared to the Modified-Booth array multiplier and to the initial multiplexer-based array scheme. The compared designs are coded in VHDL and synthesized using the TSMC 0.13μm technology library. The synthesis results of critical time and area show 11-22% improvement in critical time delay compared to the Modified-Booth array, in the expense of an area overhead of 3.8-16%. Compared to the initial multiplexerbased scheme, there is a significant improvement in terms of area and critical time.

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A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree

Cited by 44 publications

References 14 publications

Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation

Implementation of high speed processor for computing convolution sum for DSP applications

A high-speed radix-4 multiplexer-based array multiplier

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