A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

Nishikawa, Takafumi; Takahashi, Masafumi; Hamada, M.; Takayanagi, T.; Arakida, Hideho; Machida, Nobuya; Yamamoto, Hideki; Fujiyoshi, Toshihide; Yamagishi, O.; Samata, T.; Asano, A.; Terazawa, T.; Ohmori, Kenji; Shirakura, J.; Watanabe, Yoshinori; Nakamura, Hiroki; Minami, Shigenobu; Kuroda, Tadahiro; Furuyama, T.

doi:10.1109/4.881219

Cited by 64 publications

(28 citation statements)

References 2 publications

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“…The conventional two-stage MB pipelined architecture [17], [18] is widely adopted in the prior hard-wired video encoder. Two MBs are processed simultaneously by the prediction engine (ME only) and the block engine (BE, including MC, reconstruction loop, and entropy coding) in pipelined manner.…”

Section: Previous Work and Problem Definitionmentioning

confidence: 99%

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Chen

Chien

Huang

et al. 2006

IEEE Trans. Circuits Syst. Video Technol.

252

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Abstract-H.264/AVC significantly outperforms previous video coding standards with many new coding tools. However, the better performance comes at the price of the extraordinarily huge computational complexity and memory access requirement, which makes it difficult to design a hardwired encoder for realtime applications. In addition, due to the complex, sequential, and highly data-dependent characteristics of the essential algorithms in H.264/AVC, both the pipelining and the parallel processing techniques are constrained to be employed. The hardware utilization and throughput are also decreased because of the block/MB/frame-level reconstruction loops. In this paper, we describe our techniques to design the H.264/AVC video encoder for HDTV applications. On the system design level, in consideration of the characteristics of the key components and the reconstruction loops, the four-stage macroblock pipelined system architecture is first proposed with an efficient scheduling and memory hierarchy. On the module design level, the design considerations of the significant modules are addressed followed by the hardware architectures, including low-bandwidth integer motion estimation, parallel fractional motion estimation, reconfigurable intrapredictor generator, dual-buffer block-pipelined entropy coder, and deblocking filter. With these techniques, the prototype chip of the efficient H.264/AVC encoder is implemented with 922.8 K logic gates and 34.72-KB SRAM at 108-MHz operation frequency. Index Terms-ISO/IEC

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Section: Previous Work and Problem Definitionmentioning

confidence: 99%

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Chen

Chien

Huang

et al. 2006

IEEE Trans. Circuits Syst. Video Technol.

252

View full text Add to dashboard Cite

show abstract

“…Reduction in self-refresh current is achieved by blocking the activation of a non-used block in a memory bank. The partial array self-refresh is already supported by Mobile DRAM [14], Cellular RAM, etc. The main problem is how to distinguish the unused blocks in array?…”

Section: Related Reseachmentioning

confidence: 99%

Handheld System Energy Reduction by OS-Driven Refresh

Moshnyaga

Reinman

et al. 2006

Lecture Notes in Computer Science

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Abstract. Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy of memory system, which unlike others, lowers energy of refresh operation in DRAM. The approach is based on two key ideas: (1) DRAM-based flash cache that keeps dirty pages to reduce the number of accesses to flash memory; and (2) OS-controlled page allocation/aging to stop the refresh operations in banks, whose pages are clean and not accessed for a long time. Simulations show that by using this technique we can decrease the overall energy consumption of DRAM/flash memory on video applications by 8-26% while reducing the DRAM refresh energy by 59-74%.

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“…In [4], it is a full dedicated hardware video codec design. It uses MVFAST for ME with search range - [5], it is a platform-based video/speech codec design. It uses 3-step hierarchical search for ME with search range -32∼+31.5.…”

Section: Methodsmentioning

confidence: 99%

“…Lack of potential for future modification of advanced algorithms and higher design effort are disadvantages. Hence, some [5] [6] adopted the hybrid software/hardware co-design to compromise the performance and flexibility.…”

Section: Introductionmentioning

confidence: 99%

Platform-based MPEG-4 video encoder SoC design

Chang¹,

Chao²,

Chen³

IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.

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An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The costefficient video encoder SOC consumes 256.8mW at 40MHz and achieves real-time encoding of 30 CIF (352x288) frames per second.

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A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM

Cited by 64 publications

References 2 publications

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder

Handheld System Energy Reduction by OS-Driven Refresh

Platform-based MPEG-4 video encoder SoC design

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