A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 mu m CMOS

Lu, F.; Samueli, H.

doi:10.1109/4.210000

Cited by 27 publications

(5 citation statements)

References 10 publications

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“…An LSI implementation of the circuit for this purpose has been considered [29]. This LSI equalizer, however, essentially assumes a continuous-time system such as frequency division multiple access (FDMA), and it is difficult to apply the configuration efficiently to a burst system.…”

Section: Introductionmentioning

confidence: 99%

High-speed QVLMS-MLSE equalizer for mobile communications

Denno

Saito

1999

Electron. Comm. Jpn. Pt. I

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Section: Introductionmentioning

confidence: 99%

High-speed QVLMS-MLSE equalizer for mobile communications

Denno

Saito

1999

Electron. Comm. Jpn. Pt. I

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“…In practice, an LSI implementation of DFE is considered, aiming at application to high-speed wireless land communications [23]. In the application of the adaptive equalizer to burst signal transmission system such as TDMA, fast synchronization must be realized from the viewpoint of slot efficiency.…”

Section: Introductionmentioning

confidence: 99%

Design and performance of 32-kbit/s ?/4-QPSK VLMS MLSE equalizer

Denno¹,

Saito²

2000

Electron. Comm. Jpn. Pt. I

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“…D IGITAL communications systems are currently being developed for high-bit rate transmission over bandlimited channels. These applications include asymmetric digital subscriber loop [8], [22] (ADSL), high-speed digital subscriber loop (HDSL) [20], [26], [45], very high-speed digital subscriber loop (VHDSL) [7], [17], ATM-LAN [18] and interactive multimedia television (IMTV) [19], high-density magnetic recording [9], wireless systems [1], and digital highdefinition TV (HDTV) transmission [29], [30]. In each of these applications, the bandlimited nature of the channel and the required performance levels necessitate the use of highly complex digital communications algorithms.…”

mentioning

confidence: 99%

Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN

Shanbhag

Goel

1997

IEEE Trans. Signal Process.

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In this paper, we present low-power and highspeed algorithms and architectures for complex adaptive filters. These architectures have been derived via the application of algebraic and algorithm transformations. The strength reduction transformation is applied at the algorithmic level as opposed to the traditional application at the architectural level. This results in a power reduction by 21% as compared with the traditional cross-coupled structure. A fine-grained pipelined architecture for the strength-reduced algorithm is then developed via the relaxed lookahead transformation. This technique, which is an approximation of the conventional lookahead computation, maintains the functionality of the algorithm rather than the input-output behavior. Convergence analysis of the proposed architecture has been presented and supported via simulation results. The pipelined architecture allows high-speed operation with negligible hardware overhead. It also enables an additional power savings of 39 to 69% when combined with power-supply reduction. Thus, an overall power reduction ranging from 60-90% over the traditional cross-coupled architecture is achieved. The proposed architecture is then employed as a receive equalizer in a communication system for a data rate of 51.84 Mb/s over 100 m of UTP-3 wiring in an ATM-LAN environment. Simulation results indicate that speedups of up to 156 can be achieved with about a 0.8-dB loss in performance.

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A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 mu m CMOS

Cited by 27 publications

References 10 publications

High-speed QVLMS-MLSE equalizer for mobile communications

High-speed QVLMS-MLSE equalizer for mobile communications

Design and performance of 32-kbit/s ?/4-QPSK VLMS MLSE equalizer

Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN

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