A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer

Mitomo, Toshiya; Fujimoto, Ryuichi; Ono, Nobutaka; Tachibana, Ryoichi; Hoshino, H.; Yoshihara, Yoshinobu; Tsutsumi, Yuji; Seto, I.

doi:10.1109/jssc.2008.917557

Cited by 85 publications

(21 citation statements)

References 8 publications

(4 reference statements)

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“…The total power consumption is 30 mW, since 26 mA from V G ¼ 700 mV and 10 mA from V DD ¼ 1.2 V are drawn. Table 1 shows the comparison between the measured performance of the presented design and the other recently published 60 GHz 90 nm CMOS LNAs ( [10][11][12][13][14][15]). It can be seen as our design is in line with the state of the art in LNA design.…”

Section: V M E a S U R E M E N T S V E R S U S S I M U L A T I O N Smentioning

confidence: 99%

A 60 GHz fully differential LNA in 90 nm CMOS technology

Malignaggi

Hamidian

Boeck

2013

Int. j. microw. wirel. technol.

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The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm 2 pads included. The detailed design procedure and the achieved measurement results are presented in this work.

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Section: V M E a S U R E M E N T S V E R S U S S I M U L A T I O N Smentioning

confidence: 99%

A 60 GHz fully differential LNA in 90 nm CMOS technology

Malignaggi

Hamidian

Boeck

2013

Int. j. microw. wirel. technol.

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“…A PLL based on a charge pump is often preferred over other synthesizer alternatives, because it exhibits a wide capture range with no systematic phase offset and arguably provides one of the simplest and most effective design platforms [9][10][11][12][13][14]. The Charge Pump based PLL also provides flexible design tradeoffs by decoupling various design parameters such as the loop bandwidth, damping factor and lock range [22].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of Charge Pumps for Telecommunication Applications

Kalenteridis

Papathanasiou

Siskos

2010

IFIP Advances in Information and Communication Technology

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Abstract. This chapter addresses modern telecommunication integrated circuits from the synthesizer focal point; in particular it concentrates at the analysis and the design of integrated charge pump circuit blocks. It presents an overview of charge pump topologies in addition to a coherent analysis of the associated benefits and shortcomings of all circuit alternatives. Moreover a novel favorable charge pump combining current steering techniques with well utilized unity gain buffers in a novel, noiseless feedback scheme, is introduced to improve on switching speed, inherent charge pump ac noise, dead-zone interval, therefore overall steady state aliased loop noise; while on the other hand this charge pump exhibits superb DC matching characteristics in a wide output voltage range. Furthermore a well documented estimation of the active devices that contributes mostly to the overall charge pump noise performance is presented. Also an associated mathematical analysis concerning the frequency content of the charge pump noise current is given. This proposed topology manifests its applicability to charge pump alternatives, as it is demonstrated by the associated simulation results from a 0.18μm design. Because of the low-noise and accurate properties of this improved charge pump, it is ideally suited to modern telecommunication standards synthesizer realizations.

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“…In [3] and [4], an antenna gain around dBi was measured for a dipole antenna, far below its optimal value.…”

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confidence: 97%

A 60-GHz CPW-Fed High-Gain and Broadband Integrated Horn Antenna

Pan

Ponchak

et al. 2009

IEEE Trans. Antennas Propagat.

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Abstract-An integrated horn antenna is presented for 60-GHz WPAN applications. Compared with other types of antenna for 60-GHz WPAN applications, an integrated horn antenna features wide bandwidth and high gain. This integrated H-plane horn is elevated on the top of the substrate using CMOS-compatible microfabrication steps. Antenna efficiency is greatly improved after eliminating dielectric loss. This antenna is excited using an integrated vertical current probe connected with a coplanar-waveguide (CPW) by surface micromachining technologies. The lower part of the horn is constructed by rows of metallized pillars. The upper part and the top wall are built by stacking two layers of micromachined silicon wafers. The horn bottom is formed by metalizing the substrate's top surface. A prototype antenna is designed, fabricated, and characterized. Simulation and measurement results have shown wide input matching bandwidth and radiation bandwidth. The measured radiation pattern agrees well with the simulated one, demonstrating a gain as high as 14.6 dBi.

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A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer

Cited by 85 publications

References 8 publications

A 60 GHz fully differential LNA in 90 nm CMOS technology

A 60 GHz fully differential LNA in 90 nm CMOS technology

Analysis and Design of Charge Pumps for Telecommunication Applications

A 60-GHz CPW-Fed High-Gain and Broadband Integrated Horn Antenna

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