A 6-ns 256-kb BiCMOS TTL SRAM

Akioka, T.; Hiraishi, A.; Yamauchi, Tsuyoshi; Yokoyama, Yuji; Takahashi, Susumu; Iwamura, M.; Kobayashi, Yutaka; Ide, Akira; Gotou, N.; Onozawa, K.; Uchida, Hideaki

doi:10.1109/4.75033

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Cited by 6 publications

(1 citation statement)

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“…Table 3 shows a comparison of both circuits. In the conventional common collector circuit (a) [5], amplification is carried out in the PSA. Therefore, the signal amplitude in the data line can be set small.…”

Section: Sense Systemmentioning

confidence: 99%

High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM

Emori

Suzuki

Yukutake

et al. 1998

Electron. Comm. Jpn. Pt. II

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Section: Sense Systemmentioning

confidence: 99%

High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM

Emori

Suzuki

Yukutake

et al. 1998

Electron. Comm. Jpn. Pt. II

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A 5‐ns 32 K ×8/×9 bi‐CMOS TTL SRAM with alternated bit line load architecture

Ohbayashi

Shiomi

Matsuo

et al. 1994

Electron Comm Jpn Pt II

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An ultrahigh‐speed 32 K ×8/×9 TTL bi‐CMOS SRAM with a 5‐ns standard access time was developed using a five‐layer polysilicon/two‐layer aluminum 0.6‐μm bi‐CMOS process with 4.2 × 5.6‐μm2 4‐M SRAM‐class small‐size memory cells, ultrahigh capacity, self‐aligned bipolar electrodes with 18.5‐GHz cutoff frequency and 0.6‐μm/0.7‐μm (nMOS/pMOS) gate‐length MOS transistors. This fast access time was achieved by using center power pin‐out to reduce output noise, a major problem in the TTL SRAM, together with alternated bit line load architecture, a memory array architecture well suited to center power pin‐out. Also used were a bit‐line load circuit for rapid precharging of the bit line and a high‐speed wired‐OR column‐sensing circuit.

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Digital Design

Raje¹

1993

BiCMOS Technology and Applications

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A 6-ns 256-kb BiCMOS TTL SRAM

Cited by 6 publications

References 6 publications

High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM

High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM

A 5‐ns 32 K ×8/×9 bi‐CMOS TTL SRAM with alternated bit line load architecture

Digital Design

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