A 6.78-MHz Robust WPT System with Inductive Link Bandwidth Extended for cm-Sized Implantable Medical Devices

Karimi, Mousa; Jouaicha, Hicham; Lellouche, François; Bouchard, Pierre; Gosselin, Benoît

doi:10.1109/embc44109.2020.9175714

Cited by 10 publications

(5 citation statements)

References 12 publications

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“…1(b), the red curve shows the currents flowing into the circuit during the deadtime, in which I L( peak) is equal to I Load + (I L /2). According to (6), I L( peak) can be defined by:…”

Section: Optimal Deadtime Mathematical Analysismentioning

confidence: 99%

“…Power converters are ubiquitous in industrial and consumer electronics. They are employed in so many applications, from smartphones, tablets, and headphones [3], [4], to TV sets, car electronics, wireless power chargers for electric vehicle [5], [6], public fitness equipment [7], and wearable medical devices [8]. Power converters, such as DC-DC converters, bridges (half and full), and class-D power amplifiers, must present high efficiency and power density [9]- [12].…”

Section: Introductionmentioning

confidence: 99%

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A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters

Karimi
¹
,

Ali
²
,

Aghajani
³

et al. 2022

IEEE Trans. Circuits Syst. I
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This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads (C L ) and operating frequencies ( f s ). The circuit consumed a power between 610 µW and 850 µW across the measured deadtime ranges while C L = 12 pF, V dd = 3.3 V, and f s = 200 kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of 150µ m × 260µm. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum T DLH and optimal T DHL at I Load = 25 mA is improved by 12% compared to a converter with a fixed deadtime of T DLH = T DHL = 12 ns.

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“…1(b), the red curve shows the currents flowing into the circuit during the deadtime, in which I L( peak) is equal to I Load + (I L /2). According to (6), I L( peak) can be defined by:…”

Section: Optimal Deadtime Mathematical Analysismentioning
confidence: 99%

Section: Introductionmentioning
confidence: 99%

A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters
Karimi
¹
,
Ali
²
,
Aghajani
³

et al. 2022
IEEE Trans. Circuits Syst. I
Self Cite
5
0
0
0
View full text Add to dashboard Cite

show abstract

“…SoCs frequently use multiple voltage supply and signal levels inside their various building blocks [15]- [18]. Using multiple technologies operating at various supply voltages within the same SiP can decrease fabrication cost and power consumption [19]- [21].…”

Section: Introductionmentioning
confidence: 99%

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source
Karimi
¹
,
Ali
²
,
Hassan
³

et al. 2022
IEEE Access
3
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A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 µm CMOS technology occupies a silicon area of only 25 µm×25 µm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, VDDL=0.8 V, and a capacitive load of CL=0.1 pF.

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“…Level shifters, whether up or down, are key building blocks in integrated electronic systems, including System-on-Chip (SoC), and System-in-Package (SiP) applications [1]- [6]. Fig.…”

Section: Introductionmentioning
confidence: 99%

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications
Karimi
¹
,
Ali
²
,
Hassan
³

et al. 2021
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
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A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35-µm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diodesupercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108.9μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 µm×100 µm.

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A 6.78-MHz Robust WPT System with Inductive Link Bandwidth Extended for cm-Sized Implantable Medical Devices

Cited by 10 publications

References 12 publications

A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters

A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

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