A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS

Li, Zhenghao; Tang, Minzhe; Fan, Taiyang; Pan, Quan

doi:10.1109/tcsii.2021.3074384

Cited by 10 publications

(3 citation statements)

References 15 publications

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“…[63] Southern University of Science and Technology demonstrated an 024201-5 CMOS process optical receiver analog front-end. [64] Wuhan University designed a 25 Gb/s inductorless optical receiver, with a high sensitivity and wide dynamic range. [65] (a) (b) Fig.…”

Section: The 2d Integrationmentioning

confidence: 99%

Silicon-based optoelectronic heterogeneous integration for optical interconnection

Li 李,

Zhang 张

et al. 2024

Chinese Phys. B

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The performance of optical interconnection has improved dramatically in recent years. Silicon-based optoelectronic heterogeneous integration is the key enabler to achieve high performance optical interconnection, which not only provides the optical gain which is absent from native Si substrates and enables complete photonic functionalities on chip, but also improves the system performance through advanced heterogeneous integrated packaging. This paper reviews recent progress of silicon-based optoelectronic heterogeneous integration in high performance optical interconnection. The research status, development trend and application of ultra-low loss optical waveguides, high-speed detectors, high-speed modulators, lasers and 2D, 2.5D, 3D and monolithic integration are focused on.

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Section: The 2d Integrationmentioning

confidence: 99%

Silicon-based optoelectronic heterogeneous integration for optical interconnection

Li 李,

Zhang 张

et al. 2024

Chinese Phys. B

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“…To satisfy the stringent bandwidth requirement while improving the spectral efficiency, IEEE 802.3bs recommends PAM4 signaling to fulfill 200/400 Gb/s Ethernet by employing 4×50 Gb/s and 8×50 Gb/s multi-channel links [3,4]. The PAM4 signaling encodes the most significant bit (MSB) and the least significant bit (LSB), into one single symbol, thus enhancing the spectral efficiency and mitigating the bandwidth limitation for both channel and front-end circuit [5,6]. Nevertheless, the PAM4 signaling exhibits a more severe inter-symbol interference (ISI) due to the in-trinsic 9.5 dB signal-to-noise ratio (SNR) penalty [7,8] and 12 different transitions compared to NRZ format.…”

Section: Introductionmentioning

confidence: 99%

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

IEICE Electron. Express

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Aiming at the jitter issue in four-level pulse amplitude modulation (PAM4) receive link, the key causes related to the non-ideal effects of channel and data decision were analyzed, and a modified PAM4 receiver architecture was proposed. An analog equalizer with extra mid-frequency compensation and 1-tap decision-feedback equalizer were incorporated to minimize the inter-symbol interference. To alleviate the timing constraints in DFE, the feedback loop of slicer was optimized. The post-simulation results based on TSMC 28 nm CMOS process indicate that the proposed 50 Gb/s PAM4 receiver functions well over a channel with 12 dB loss at Nyquist frequency. The peak-to-peak jitters of two restored NRZ signals are 1.5 ps and 2.5 ps, respectively.

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“…Generally, the FR-4 backplane channel has more serious insertion loss at high frequency, while the traditional CTLE structure cannot pro-vide sufficient gain. Ref [19] uses the inductance peaking technology to expand the bandwidth and improve the peaking gain, but the traditional inductance is difficult to integrate and the impedance is fixed. In addition, considering that the channel loss will be affected by the environment and the non-ideal characteristics like skin effect, Ref [20] proposes a CTLE with adjustable zero-pole based on the source degradation structure, which will better adjust the CTLE high frequency gain.…”

Section: Introductionmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

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This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

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A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS

Cited by 10 publications

References 15 publications

Silicon-based optoelectronic heterogeneous integration for optical interconnection

Silicon-based optoelectronic heterogeneous integration for optical interconnection

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

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