A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI

Pawłowski, Robert; Krimer, Evgeni; Crop, Joseph; Postman, Jacob; Moezzi-Madani, Nariman; Erez, Mattan; Chiang, Patrick

doi:10.1109/isscc.2012.6177105

Cited by 20 publications

(34 citation statements)

References 2 publications

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“…Beyond instruction-level reuse, various techniques have been proposed to mitigate the variation-induced timing errors, including adaptive management of guardbanding through 'predict-and-prevent' mechanisms [16,17,22,18,19], and 'detect-then-correct' mechanisms [6,7,9,11]. A brief review of the main concepts and their embodiments follows.…”

Section: Related Workmentioning

confidence: 99%

“…Detect-then-correct technique for SIMD architectures decouples the lanes through private queues that prevent error events in any single lane from stalling all other lanes [11]. This enables each lane to recover from errors independently.…”

Section: Related Workmentioning

confidence: 99%

“…Further, the decouple queue relies on the recovery based on the global clock-gating which involves stalling the entire lane. This causes one cycle recovery penalty over a two-stage execution unit [11]. However, propagating a global stall signal over a deep GPGPU pipeline [10] is expensive.…”

Section: Related Workmentioning

confidence: 99%

“…Effectively, these energy-hungry highlatency pipelines are prone to inefficiencies under timing errors. Similarly, in vertically expanded pipelines, there is a significant performance drop in a 10-lane SIMD architecture as single-stage-error probabilities increase [11]. In the lock-step execution, any error within any of the lanes will cause a global stall and force recovery of the entire SIMD pipeline.…”

Section: Contents 1 Introduction 4 1 Introductionmentioning

confidence: 99%

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Temporal memoization for energy-efficient timing error recovery in GPGPUs

Rahimi

Benini

Gupta

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Manufacturing and environmental variability lead to timing errors in computing systems that are typically corrected by error detection and correction mechanisms at the circuit level. The cost and speed of recovery can be improved by memoization-based optimization methods that exploit spatial or temporal parallelisms in suitable computing fabrics such as general-purpose graphics processing units (GPGPUs). We propose here a temporal memoization technique for use in floating-point units (FPUs) in GPGPUs that uses value locality inside data-parallel programs. The technique recalls (memorizes) the context of error-free execution of an instruction on a FPU. Therefore, it avoids redundant execution and saves energy for FPU. To enable scalable and independent recovery, a single-cycle lookup table (LUT) is tightly coupled to every FPU to maintain contexts of recent errorfree executions. The LUT reuses these memorized contexts to exactly, or approximately, correct errant FP instructions based on application needs. In real-world applications, the temporal memoization technique achieves an average energy saving of 13%-25% for a wide range of timing error rates (0%-4%) and outperforms recent advances in resilient architectures. This technique also enhances robustness in the voltage overscaling regime and achieves relative average energy saving of 44% with 11% voltage overscaling.2

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Contents 1 Introduction 4 1 Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Temporal memoization for energy-efficient timing error recovery in GPGPUs

Rahimi

Benini

Gupta

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…Then, recovery mechanisms compensate the error while incurring extra RCPE cost. Their cost of recovery is shown to be high in face of frequent timing errors, especially so in aggressive voltage over-scaling and near-threshold computation [13]. Moreover, these per-core detection-correction mechanisms that seek to act for every instance of timing error may be inefficient in the system-level that feature a cluster of tightly-coupled processors.…”

Section: Related Workmentioning

confidence: 99%

Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters

Rahimi

Marongiu

Burgio

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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We present a variation-tolerant tasking technique for tightlycoupled shared memory processor clusters that relies upon modeling advance across the hardware/software interface. This is implemented as an extension to the OpenMP 3.0 tasking programming model. Using the notion of Task-Level Vulnerability (TLV) proposed here, we capture dynamic variations caused by circuitlevel variability as a high-level software knowledge. This is accomplished through a variation-aware hardware/software codesign where: (i) Hardware features variability monitors in conjunction with online per-core characterization of TLV metadata; (ii) Software supports a Task-level Errant Instruction Management (TEIM) technique to utilize TLV metadata in the runtime OpenMP task scheduler. This method greatly reduces the number of recovery cycles compared to the baseline scheduler of OpenMP [22], consequently instruction per cycle (IPC) of a 16-core processor cluster is increased up to 1.51× (1.17× on average). We evaluate the effectiveness of our approach with various number of cores (4,8,12,16), and across a wide temperature range(∆T=90°C).

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A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI

Cited by 20 publications

References 2 publications

Temporal memoization for energy-efficient timing error recovery in GPGPUs

Temporal memoization for energy-efficient timing error recovery in GPGPUs

Variation-tolerant OpenMP Tasking on Tightly-coupled Processor Clusters

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