A 512GOPS Fully-Programmable Digital Image Processor with full HD 1080p Processing Capabilities

IEEE J. Solid-State Circuits

Park

et al. 2013

Abstract-A heterogeneous multi-core processor is proposed to achieve real-time dynamic object recognition on HD 720p video streams. The context-aware visual attention model is proposed to reduce the required computing power for HD object recognition based on enhanced attention accuracy. In order to realize real-time execution of the proposed algorithm, the processor adopts a 5-stage task-level pipeline that maximizes the utilization of its 31 heterogeneous cores, comprising four simultaneous multithreading feature extraction clusters, a cache-based feature matching processor and a machine learning engine. Dynamic resource management is applied to adaptively tune thread allocation and power management during execution based on the detected amount of tasks and hardware utilization to increase energy efficiency. As a result, the 32 mm chip, fabricated in 0.13 m CMOS technology, achieves 30 frame/sec with 342 8-bit GOPS peak performance and 320 mW average power dissipation, which are a 2.72 times performance improvement and 2.54 times per-pixel energy reduction compared to the previous state-of-the-art.Index Terms-Multi-core processor, object recognition, scale invariant feature transform, heterogeneous, low power processor, dynamic resource management, dynamic voltage and frequency scaling. GLOSSARY OF ABBREVIATIONS GOPS

Section: A Chip Summarymentioning

confidence: 98%

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams

IEEE J. Solid-State Circuits

Park

et al. 2013

“…5 shows the proposed NoC-based heterogeneous multicore architecture for real-time object recognition, which consists of a main processor, a visual attention engine (VAE), a matching accelerator (MA), linear array of programmable edge clusters (PECs) and an external interface. Different from a conventional massively parallel SIMD architecture [8]- [11], the linear array of N simple PEs with nearest neighbor connections is equally divided into M PECs, each of which contains a linear array of N/M PEs and a controller to allow independent processing of each PEC. The ARM10-compatible 32-bit main processor controls the overall system operations.…”

Section: Proposed Multicore Architecturementioning

confidence: 99%

“…Several parallel processing architectures have been presented for vision applications. Massively parallel single-instructionmultiple-data (MP-SIMD) processors with linear processor array, such as Internet message access protocol [8] and Xetal [9] have been developed for low-level vision processing [10], [11]. However, these processors are not suitable for higher-level vision applications that exhibit more irregular and data-dependent behavior than low-level operations.…”

mentioning

confidence: 99%

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition

Lee

IEEE Trans. Circuits Syst. Video Technol.

et al. 2009

Abstract-As object recognition requires huge computation power to deal with complex image processing tasks, it is very challenging to meet real-time processing demands under low-power constraints for embedded systems. In this paper, a configurable heterogeneous multicore architecture with a dual-mode linear processor array and a cellular neural network on the networkon-chip platform is presented for real-time object recognition. The bio-inspired attention-based object recognition algorithm is devised to reduce computational complexity of the object recognition. The cellular neural network is utilized to accelerate the visual attention algorithm for selecting salient image regions rapidly. The dual-mode parallel processor is configured into single instruction, multiple data (SIMD) or multiple-instructionmultiple-data modes to perform data-intensive image processing operations while exploiting pixel-level and feature-level parallelisms required for the attention-based object recognition. The algorithm's hybrid parallelization strategy on the proposed architecture is adopted to obtain maximum performance improvement. The performance analysis results, using a cycle-accurate architecture simulator, show that the proposed architecture achieves a speedup of 2.8 times for the target algorithm over conventional massively parallel SIMD architecture at low hardware cost overhead. A prototype chip of the proposed architecture, fabricated in 0.13 µm complementary metal-oxidesemiconductor technology, achieves 22 frames/s real-time object recognition with less than 600 mW power consumption.

Journal of Information Processing

“…In the Full HD case, if the working frequency of the processor is 400 MHz, the allowable processing time for each pixel is 6.43 cycles (400 M/(1,920 × 1,080 × 30)). Uniprocessor architecture is not efficient in supporting such a high performance requirement; therefore, multiprocessor-based architectures are being adopted [3], [4], [5] to support high com- In designing a high performance multiprocessor architecture for the image processing engine, the capability of processing element and communication architecture which is used to connect the processing elements are essential issues. The common hardware types of processing element on the market can be classified into ASIC, reconfigurable ASIC, Application specific instructionset processor (ASIP), DSP and general purpose processor (GPP).…”

Section: Introductionmentioning

confidence: 99%

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing

Liao

Asri

Isshiki

et al. 2013

An image processing engine is an important component in generating high quality images in video systems. Processing during capture and display are non-standard and vary from case by case, hence, the flexibility of image processing engines has turned out to be an important issue. The conventional hardware type of image processing engine such as an Application Specific Integrated Circuit (ASIC) is not applicable for this case. In order to increase design reusability and ease time-to-market pressures, Application Specific Instruction-set Processors (ASIP) which provide high flexibility and high computational efficiency have emerged as a promising solution. In this paper, we present two ASIPs. PXL ASIP, which has a reconfigurable multi bank memory module and an SIMD type computation pipeline, is designed for pixel level image processing, while 2D ASIP, which has slide register module and reconfigurable ALU modules, is designed for 2D image processing. PXL ASIP can perform 4 to 10 times faster compared to its base processor, and 2D ASIP can perform 5 to 43 times faster compared to its base processor.