A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements

Lee

IEEE Trans. Circuits Syst. Video Technol.

et al. 2009

Abstract-As object recognition requires huge computation power to deal with complex image processing tasks, it is very challenging to meet real-time processing demands under low-power constraints for embedded systems. In this paper, a configurable heterogeneous multicore architecture with a dual-mode linear processor array and a cellular neural network on the networkon-chip platform is presented for real-time object recognition. The bio-inspired attention-based object recognition algorithm is devised to reduce computational complexity of the object recognition. The cellular neural network is utilized to accelerate the visual attention algorithm for selecting salient image regions rapidly. The dual-mode parallel processor is configured into single instruction, multiple data (SIMD) or multiple-instructionmultiple-data modes to perform data-intensive image processing operations while exploiting pixel-level and feature-level parallelisms required for the attention-based object recognition. The algorithm's hybrid parallelization strategy on the proposed architecture is adopted to obtain maximum performance improvement. The performance analysis results, using a cycle-accurate architecture simulator, show that the proposed architecture achieves a speedup of 2.8 times for the target algorithm over conventional massively parallel SIMD architecture at low hardware cost overhead. A prototype chip of the proposed architecture, fabricated in 0.13 µm complementary metal-oxidesemiconductor technology, achieves 22 frames/s real-time object recognition with less than 600 mW power consumption.

Section: Proposed Multicore Architecturementioning

confidence: 99%

mentioning

confidence: 99%

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition

Lee

IEEE Trans. Circuits Syst. Video Technol.

et al. 2009

“…CLIP7A is also designed for general-purpose applications. IMAP-CE is another SIMD 1-D array processor [17]. It is designed for video recognition, and it is composed of 128 VLIW processors and can achieve a high processing capability of 51.2-GOPS.…”

Section: Comparison With Previous 1-d Array Processor Architecturesmentioning

confidence: 99%

“…The architectures of the processing elements and interconnection units are optimized for morphological image processing. In order to lower the I/O bandwidth requirement, it is not an SIMD array processor [8,17]. The high performance is achieved by many processors working in a pipeline with different assigned works, like Cytocomputer [18].…”

Section: Comparison With Previous 1-d Array Processor Architecturesmentioning

confidence: 99%

Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation

Chien

Chen

2008

J Sign Process Syst

Video object segmentation is an important pre-processing task for many video analysis systems. To achieve the requirement of real-time video analysis, hardware acceleration is required. In this paper, after analyzing existing video object segmentation algorithms, it is found that most of the core operations can be implemented with simple morphology operations. Therefore, with the concepts of morphological image processing element array and stream processing, a reconfigurable morphological image processing accelerator is proposed, where by the proposed instruction set, the operation of each processing element can be controlled, and the interconnection between processing elements can also be reconfigured. Simulation results show that most of the core operations of video object segmentation can be supported by the accelerator by only changing the instructions. A prototype chip is designed to support real-time change-detection-andbackground-registration based video object segmentation algorithm. This chip incorporates eight macro processing elements and can support a processing capacity of 6,200 9-bit morphological operations per second on a SIF image. Furthermore, with the proposed tiling and pipelined-parallel techniques, a realtime watershed transform can be achieved using 32 macro processing elements.

“…Massively parallel SIMD processors with a number of PEs were presented to exploit data-level parallelism in a 2-D image array of pixels [3,4]. However, these processors focus on only the low-level image processing operations like image filtering and thus they are not suitable for object-level parallelism, which is essential for the object recognition.…”

Section: Introductionmentioning

confidence: 99%

A 76.8 GB/s 46 mW low-latency network-on-chip for real-time object recognition processor

2008 IEEE Asian Solid-State Circuits Conference

Lee

et al. 2008

Abstract-A 76.8 GB/s 46 mW low-latency network-on-chip (NoC) provides a communication platform for a real-time object recognition processor. The tree-based topology NoC with three crossbar switches is designed for low-latency by adopting dualchannel and adaptive switching. The NoC can be dynamically configured to exploit both data-level and object-level parallelism on the object recognition processor. FLIT-level clock gating and packet-based power management scheme are employed for low power consumption. The NoC is implemented in 0.13µm CMOS process and provides 76.8 GB/s aggregated bandwidth at 400MHz with 2-clock cycle latency while dissipating 46 mW at 1.2 V.