A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket

Lamb, Amanda; Riley, Liz; Hall, S.; Kunz, V.D.; Groot, C.H. de; Ashburn, P.

doi:10.1109/essderc.2001.195272

Cited by 6 publications

(5 citation statements)

References 5 publications

(5 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The formed oxide layer in the source and drain regions is then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode to form the dielectric pillar (plug) and a channel region between the source and drain regions. Moreover, the integration of dielectric pillars on vertical architecture has also been reported and its fabrication schemes have been discussed in [10][11][12].…”

Section: Device Feasibilitymentioning

confidence: 99%

See 1 more Smart Citation

Two-dimensional analytical model to characterize novel MOSFET architecture: insulated shallow extension MOSFET

Kaur

Chaujar

Saxena

et al. 2007

Semicond. Sci. Technol.

View full text Add to dashboard Cite

In this paper, a computationally efficient model using evanescent mode analyses for solving two-dimensional Poisson's equation in the channel region has been presented for an accurate prediction of (a) surface potential, (b) electric field, (c) I DS -V GS characteristics, (d) threshold voltage, (e) transconductance and (f) drain conductance of insulated shallow extension MOSFET. The important short channel device features, drain induced barrier lowering (implemented via the voltage doping transformation method), channel length modulation and velocity saturation/overshoot, have been included in the model in a physically consistent manner. The obtained analytical results have been verified by ATLAS 2D: device simulation software.

show abstract

Section: Device Feasibilitymentioning

confidence: 99%

“…The electric field component along the channel (i.e. in the xdirection) is determined by differentiating (10) with respect to x and is given as…”

Section: Electric Field Distribution Modelmentioning

confidence: 99%

Two-dimensional analytical model to characterize novel MOSFET architecture: insulated shallow extension MOSFET

Kaur

Chaujar

Saxena

et al. 2007

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…In [8], following the well implantation and gate patterning, depression in the S/D region that determines the depth of a dielectric pillar (pocket) was formed using anisotropic plasma etching. Moreover, incorporation of dielectric pillars on vertical architecture has also been reported and its fabrication schemes have been discussed in [19][20][21].…”

Section: Device Fabrication Feasibilitymentioning

confidence: 99%

Lateral channel engineered hetero material insulated shallow extension gate stack (HMISEGAS) MOSFET structure: high performance RF solution for MOS technology

Kaur

Chaujar

Saxena

et al. 2007

Semicond. Sci. Technol.

View full text Add to dashboard Cite

In this work, due to increasing interest in analog and RF applications of MOS technology, an extended study is performed using ATLAS-2D device simulation software to assess the RF performance of insulated shallow extension gate stack (ISEGAS) devices in comparison to conventional bulk devices. The paper analyzes the frequency dependence of gate transconductance and parasitic capacitances that affect various RF performance metrics. Improvement in the characteristics of ISE with hetero material gate (HMG) incorporation (HMISEGAS) is also studied. Thus, the ISE structure with the HMG architecture can revolutionize the wireless communication market on account of having enormous RF application potential and the ability to combat short channel effects-the daunting roadblock for miniaturization.

show abstract

“…We now investigate the means of addressing these three key issues. We have reported a novel vertical transistor architecture incorporating a so-called dielectric pocket [6,7] for control of short channel effects. This concept was first demonstrated successfully within a lateral architecture [8], but implementation in a vertical architecture is considerably simpler.…”

Section: Vertical Mosfetsmentioning

confidence: 99%

Recent developments in vertical MOSFETs and SiGe HBTs

Hall,

Ashburn,

Buiu

et al. 2004

JTIT

View full text Add to dashboard Cite

There is a well recognised need to introduce new materials and device architectures to Si technology to achieve the objectives set by the international roadmap. This paper summarises our work in two areas: vertical MOSFETs, which can allow increased current drive per unit area of Si chip and SiGe HBT`s in silicon-on-insulator technology, which bring together and promise to extend the very high frequency performance of SiGe HBT`s with SOI-CMOS.

show abstract

A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket

Abstract: Abstract

Cited by 6 publications

References 5 publications

Two-dimensional analytical model to characterize novel MOSFET architecture: insulated shallow extension MOSFET

Two-dimensional analytical model to characterize novel MOSFET architecture: insulated shallow extension MOSFET

Lateral channel engineered hetero material insulated shallow extension gate stack (HMISEGAS) MOSFET structure: high performance RF solution for MOS technology

Recent developments in vertical MOSFETs and SiGe HBTs

Contact Info

Product

Resources

About