A 500 MHz-to-1.2 GHz Reset Free Delay Locked Loop for Memory Controller with Hysteresis Coarse Lock Detector

Abstract

Abstract-This paper describes a reset-free delaylocked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-μm CMOS process, postlayout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 mm 2 and dissipates 16.6 mW at 1.2GHz.

27.3: 1.2 Gbps GDDR3 Physical Layer for 3D AMOLED Panel

“…The unwanted unlocking problem is eliminated by introducing hysteresis in the coarse locking operation as shown in figs. 3 and 4 [4]. The vertical axis representing the delay is divided into 3 regions: a narrow lock region, a wide lock region and an unlock region.…”

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

“…The HCLD generates a clock whose frequency is half the input's and counts edges in its every evaluation phase (Chi et al, 2011), thus it can avoid harmonic lock and stuck problems without requiring any external reset. The conventional CLD has shortcomings in speed and area.…”

A Design of Vernier Coarse-Fine Time-to-Digital Converter using Single Time Amplifier

“…It is preferred not to use a vernier delay line for reducing the mismatch of the delay buffer, but buffer delay is limited by process [1]. However vernier delay line is the only way to overcome the buffer delay limitation, so the vernier delay line method is adapted in this design to consider that PLL is widely used not only in state-of-the-art process but in many general processes [6].…”