A 500-MHz pipelined burst SRAM with improved SER immunity

Sato, H.; Wada, T.; Ohbayashi, S.; Kozaru, K.; Okamoto, Y.; Higashide, Y.; Shimizu, T.; Maki, Yasuhiko; Morimoto, R.; Otoi, H.; Koga, Tomohiro; Honda, Hiroki; Taniguchi, Makoto; Arita, Yukio; Shiomi, T.

doi:10.1109/4.799865

Cited by 23 publications

(8 citation statements)

References 3 publications

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“…In one structure, the p-well contact is of an area of 0.36 µm 2 , while in the other, the pwell contact area was increased to 2.125 µm 2 . After a single event strike of LET 40 MeVcm 2 /mg to the drain of the NMOS device in the off state occurs for the two structures, the current and voltage at the drain are plotted with respect to time.…”

Section: P-well Contact Sizementioning

confidence: 99%

“…The p-well -n-well junctions alter the single event performance of an NMOSFET built in a triplewell technology from that in dual well [1][2][3][4][5]. The single event charge collection in triplewell NMOSFETs may be higher than that in dual-well structures in some circumstances [5].…”

Section: Overviewmentioning

confidence: 99%

“…As device dimensions scale, the fact that triple well technology helps reduce charge collection at the drain of the NMOSFET by collecting charge in the n-well [1][2] does not explain the whole phenomenon of charge collection. Due to the potential redistributions at the well contacts, there are associated effects of charge injection by the source that may affect the single event performance of triple-well NMOSFETs adversely.…”

Section: Overview Of Previous Workmentioning

confidence: 99%

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Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Roy

Witulski

Schrimpf

et al. 2008

IEEE Trans. Nucl. Sci.

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Section: P-well Contact Sizementioning

confidence: 99%

Section: Overviewmentioning

confidence: 99%

Section: Overview Of Previous Workmentioning

confidence: 99%

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Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Roy

Witulski

Schrimpf

et al. 2008

IEEE Trans. Nucl. Sci.

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“…There were no significant modifications to the SRAM cell design, which resulted in a slow increase in the SER/bit and a rapid increase in the chip-level SER due to a rising number of bits per chip [88]. The system-level SER can be reduced by ECC, although some SRAM manufacturers began implementing capacitor structures such as those used in DRAM [89], [90], [91].…”

Section: Scaling Of Total Ser In Memoriesmentioning

confidence: 99%

Characterization of soft errors caused by single event upsets in CMOS processes

Karnik

Hazucha

2004

IEEE Trans.Dependable and Secure Comput.

442

211

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Abstract-Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in highperformance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

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“…We implement our safe storage cells using a six-transistor cell to maximize the static noise margin (SNM) since SNM is a good measure of the amount of spurious signal needed at the memory cell inputs to corrupt its state. The SNM of different memory cell configurations has been studied [2], showing that the 6T configuration is the best choice to maximize SNM if higher EMI tolerance system is needed [3,4].…”

Section: Introductionmentioning

confidence: 99%

TERPS: the embedded reliable processing system

Wang¹,

Rodriguez²,

Dirik³

et al.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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-TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TERPS tolerates EMI by periodically checkpointing processor state into a special safe-storage device. The detection of EMI invokes rollback, which recovers processor state from a previously check-pointed state and resumes normal execution. Rollback results in loss of performance dictated by the EMI duration; TERPS ensures forward progress of the system provided EMI events are separated by some minimum time interval (e.g., at least 5.12µ µ µ µs for our prototype processor running at 100MHz). The performance overhead of our mechanism is reasonable: 5-6% overhead when checkpointing every 128 processor cycles.

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A 500-MHz pipelined burst SRAM with improved SER immunity

Cited by 23 publications

References 3 publications

Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Single Event Mechanisms in 90 nm Triple-Well CMOS Devices

Characterization of soft errors caused by single event upsets in CMOS processes

TERPS: the embedded reliable processing system

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