A 50 MHz phase- and frequency-locked loop

Cordell, R.R.; Forney, J.B.; Dunn, C.N.; Garrett, W.

doi:10.1109/jssc.1979.1051309

Cited by 35 publications

(12 citation statements)

References 4 publications

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“…Also, compared with the frequency acquisition circuit with an IF mixer [10], the proposed acquisition circuit has the advantages of a broader frequency acquisition range, lower current consumption, much simpler circuit configuration, and more stable frequency acquisition. Table 1 summarizes the performance comparison among different frequency acquisition circuits.…”

Section: Phase-locked Loop Circuitsmentioning

confidence: 99%

“…Hyun Park, Kang Wook Kim, Sang-Kyu Lim, and Jesoo Ko circuit [9] or an IF mixer circuit [10], the frequency acquisition circuit proposed in this paper provides better stability, faster frequency acquisition, and faster recovery time when the clock recovery circuit loses the locking state. This paper describes the circuit configurations of the 40 Gb/s CDR module, including the principle of the improved frequency acquisition circuit, and provides the experimental results.…”

Section: Introductionmentioning

confidence: 99%

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A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits

Park¹,

Kim²,

Lim³

et al. 2008

ETRI Journal

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A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence (2 31 -1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

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Section: Phase-locked Loop Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits

Park¹,

Kim²,

Lim³

et al. 2008

ETRI Journal

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“…As compared with the frequency acquisition circuit employing a sweep circuit [7], the new frequency acquisition circuit offers the following advantages: 1) since the new acquisition circuit is controlled by polarity of the quadrature phase of I and Q signals, the operation provides better stability in the presence of temperature variations; 2) the time required for frequency detection and acquisition is much faster, 3) the recovery time after temporary loss of the clock is much faster even without the clock hold circuit. Also, as compared with the frequency acquisition circuit with an IF mixer [8], the advantages of the new acquisition circuit are 1) broader frequency acquisition range, 2) lower current consumption, 3) much simpler circuit configuration, and 4) more stable frequency acquisition. To retime the clock signal for the regeneration of 40 Gb/s transmitted signals and for the demultiplexing to 10 Gb/s signals, an analog phase shifter which provides more than 360°phase shift at 40 GHz is implemented.…”

Section: B Phase-locked Loop Circuitsmentioning

confidence: 99%

“…In this paper, the performance of the PLL CR module has been further improved by adopting a new frequency acquisition circuit and a new clock hold circuit. The conventional frequency acquisition circuit was implemented with a frequency sweep circuit [7] or with an IF mixer circuit [8]. However, the new frequency acquisition circuit proposed in this paper provides broader frequency capture range, faster frequency acquisition, and lower power consumption.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits

Park

Woo

Kim³

et al. 2006

2006 IEEE MTT-S International Microwave Symposium Digest

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Significant performance improvements have been obtained with a 40 Gb/s phase-locked clock recovery (CR) module for fiber optic receivers by employing a new frequency acquisition circuit in the phase-locked loop (PLL) and a clock hold circuit. The new simple frequency acquisition circuit helps to extend the frequency lock-range, obtain faster frequency acquisition, and reduce the current consumption as compared with the conventional ones. In addition, a clock hold circuit helps to prevent the loss of the clock signal in the cases of temporary input signal loss. The measured RMS jitter of the improved PLL CR module at 40 Gb/s is about 250 fs, which is significantly better than the open-loop type CR module.

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“…This problem can be relieved by employing frequency acquisition aids such as frequency sweep, frequency discrimination [18][19][20][21][22][23], or feed-forward control [24].…”

mentioning

confidence: 99%

Improved Phase-Locked Loop Performance with Adaptive Phase Comparators

Eijselendoorn

Dulk

1982

IEEE Trans. Aerosp. Electron. Syst.

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A major problem in phase-locked loop (PLL) design is to meet the requirements of both fast signal acquisition and good synchronous mode performance. This relation is reviewed for different types of phase comparators. As a result a new phase-and-frequency comparator is proposed. This comparator is based on an up-down counter principle and can be considered as an adaptive acquisition control circuit. The analysis of a PLL with the proposed phase comparator is based on an exact calculation method for the pull-in time. It is shown that fast signal acquisition is possible without affecting the filtering properties of the loop. Experimental results are given of the acquisition behavior of a second-order type-2 loop which show a good correspondence with the theoretical analysis.

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A 50 MHz phase- and frequency-locked loop

Cited by 35 publications

References 4 publications

A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits

A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits

Performance Improvement of a 40 Gb/s PLL Clock Recovery Module Using New Frequency Acquisition and Clock Hold Circuits

Improved Phase-Locked Loop Performance with Adaptive Phase Comparators

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