A ±5-V CMOS analog multiplier

Qin, Shu; Geiger, R.L.

doi:10.1109/jssc.1987.1052866

Cited by 109 publications

(21 citation statements)

References 4 publications

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“…Again, by comparing (15) to (8), one should find the corresponding term ∆I , of the output current is given by…”

Section: Mismatch Error On the Threshold Voltagementioning

confidence: 99%

“…Conventional design technique for a CMOS analog multiplier circuit is based on the square-law characteristics of an MOS transistor [1]- [6]. A Gilbert multiplier cell [7] is first introduced in a bipolar technology, and a modified CMOS version of it is also described [8]; however, its power supply cannot be properly fitted into low voltage (≤3V) range. Few fourquadrant multipliers suitable for low supply voltages are presented in the literatures [9]- [13].…”

Section: Introductionmentioning

confidence: 99%

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±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

Jimmy

2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

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A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. It brings in the benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35µm n-well SPQM CMOS technology has a nonlinearity error less than 0.8% over ±0.5V input range under a nominal supply voltage of ±1.5V, and consumes the total power dissipation of 2.7 mW only.

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“…Again, by comparing (15) to (8), one should find the corresponding term ∆I , of the output current is given by…”

Section: Mismatch Error On the Threshold Voltagementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

Jimmy

2002

Proceedings of the 2002 International Symposium on Low Power Electronics and Design - ISLPED '02

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“…The additional device of a true Gilbert multiplier [14] sets up a constant operating current--a luxury we could not afford given the limited power supply range. For the ETANN, the total current through the synapse depends on both, the input and the weight values (figure 3d), thus adding one more variable that the adaptive algorithm must compensate.…”

Section: Analog Multiplier Cellmentioning

confidence: 99%

Implementation and performance of an analog nonvolatile neural network

Castro

Tam

Holler

1993

Analog Integr Circ Sig Process

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Abstract. An integrated circuit implementation of a fully parallel analog artificial neural network is presented. We include details of the architecture, some of the important design considerations, a description of the circuits and finally actual performance data. The electrically trainable artificial neural network (ETANN) chip incorporates 64 analog neurons and 10,240 analog synapses and utilizes a 1-gin CMOS NVM process. The network calculates the dot product between a 64-element analog input vector and a 64 × 64 nonvolatile (EEPROM based) analog synaptic weight array. These calculations occur at a rate in excess of 1.3 billion interconnections per second. All elements of the computation are stored and calculated in the analog domain and strictly in parallel. A 2:1 input and neuron multiplex mode permits rates in excess of 2 billion interconnections per second and a single-chip effective network size of 64 inputs by 128 outputs. The ETANN incorporates differential signal techniques throughout for improved noise rejection. Current summing is employed for the sum of products calculations. The chip integrates approximately 400 op amps, including variable gain stages of from 20 to 54 dB. Inevitable component to component variations due to the use of minimum dimension elements are found not to be significant for operation in an adaptive environment.

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“…Several techniques of implementing analog multipliers, using field-effect transistors (FET), have been reported. They are the variable transconductance technique [4][5][6], the voltage-controlled transconductance technique, which employs FET transistors operating in the triode region [7][8][9], techniques based on square-law characteristics of FET transistors operating in the saturation region, implementing either the quarter-square identity [10][11][12] or other algebraic identity [13,14]. For electronic signals' level control, controlled signal is multiplied by a constant voltage with the usage of the multiplier.…”

Section: Introductionmentioning

confidence: 99%