2021
DOI: 10.1109/jssc.2020.3034241
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A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications

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Cited by 18 publications
(5 citation statements)
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“…Extreme ultraviolet lithography (EUVL) is already being used for high volume manufacturing of semiconductor devices in recent years and has been a major drive in the advancement of these devices into smaller pattern sizes. [1][2][3][4][5][6] However, there are still some issues in EUVL that remain and require close attention. The occurrence of stochastic or random defects has been reported as a EUVL-specific issue and has been a research focus in the last few years.…”
Section: Introductionmentioning
confidence: 99%
“…Extreme ultraviolet lithography (EUVL) is already being used for high volume manufacturing of semiconductor devices in recent years and has been a major drive in the advancement of these devices into smaller pattern sizes. [1][2][3][4][5][6] However, there are still some issues in EUVL that remain and require close attention. The occurrence of stochastic or random defects has been reported as a EUVL-specific issue and has been a research focus in the last few years.…”
Section: Introductionmentioning
confidence: 99%
“…The resolution of photoresist materials used for semiconductor lithography has been improved and will continue to be improved to meet the market demands of highly integrated semiconductor devices. [1][2][3][4][5][6][7] However, stochastic defects such as line bridges and breaks, which are randomly generated, become the new issues on sub-20 nm half-pitch patterns. [8][9][10][11][12][13][14][15] The cause of stochastic defects is assumed to be the small and insufficient number of photons delivered to the photoresist film (compared with that in ArF immersion) [15][16][17][18] or the effect of the molecular weight of the photoresist polymer.…”
Section: Introductionmentioning
confidence: 99%
“…Thus, the peripheral and built-in write assist approaches came into being. For example, some references apply peripheral assists such as negative bitline [13,14], wordline boost [15,16], and lowering VDD [17] based on the traditional 6T cell. Still, these SRAM cells cannot support bit-interleaving, which is critical to solving the multi-bit soft error issue.…”
Section: Introductionmentioning
confidence: 99%