A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 $\mu{\hbox{m}}$ CMOS

Solda, S.; Caruso, Michele; Bevilacqua, Andrea; Gerosa, A.; Vogrig, D.; Neviani, A.

doi:10.1109/jssc.2011.2144070

Cited by 64 publications

(15 citation statements)

References 17 publications

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“…3 shows the schematic of the integrator. The integrator is located in the next stage of the squarer and is composed of the transconductance (g m ) stage, sample and hold (S/H) capacitor, and a set of control switches [4]. When the integration window (int) switches are turned on, the g m stage injects a current into the S/H capacitor, and these circuits perform the integration operation.…”

Section: Circuit Designmentioning

confidence: 99%

“…Previous squarers based on a passive self-mixer do not consume power but require an additional amplifier to obtain a conversion gain [2]. A squarer based on a pseudo-differential circuit consumes additional power to remove the dc offset of the output [3,4,5]. A squarer based on stacked NMOS and PMOS transistor pairs can save dc power consumption [6].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

CMOS energy detector based on complementary squarer circuit for non-coherent UWB receiver

Kım

Kwon

2016

IEICE Electron. Express

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This letter presents a CMOS energy detector for a non-coherent ultra-wideband receiver. The proposed complementary squarer generates differential output using the NMOS and PMOS differential cascode stage with a common-mode feedback (CMFB) circuit. The squarer achieves high gain without DC offset using complementary squarer based on symmetrical NMOS and PMOS transistor pairs with very low power consumption. The proposed squarer with the integrator is designed using the 0.11-µm CMOS technology. The designed squarer with integrator operates at 3-5 GHz and only dissipate 1 mW at a supply voltage of 1.2 V.

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Section: Circuit Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CMOS energy detector based on complementary squarer circuit for non-coherent UWB receiver

Kım

Kwon

2016

IEICE Electron. Express

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“…This implant is composed of application specific integrated circuits (ASICs) to perform 100-channel recording at a wireless data rate of 24 Mb/s, but a high power consumption (50 mW) dissipated by its FSK transmitter imposes challenges to expand its application for hundreds of channel recording. Despite wireless data telemetry for neural recording has emerged as a popular research topic during the past decade, few work has achieved very high data rate at low power consumption [9][10][11][13][14][15][16][17][18][19]. Therefore, a new paradigm for the wireless data link is desperately necessary.…”

Section: Wireless Gigabit Data Telemetry Formentioning

confidence: 99%

“…Up to date, many wireless recording systems based on both off-the-shelf components and integrated circuits (IC) have been published [7][8][9][10][11][12][13]. A 32-channel wireless recording system was reported to transmit 24 Mb/s at a distance of 20 m [8].…”

Section: Introductionmentioning

confidence: 99%

Wireless Gigabit Data Telemetry for Large-Scale Neural Recording

Kuan

Kim

et al. 2015

IEEE J. Biomed. Health Inform.

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Implantable wireless neural recording from a large ensemble of simultaneously acting neurons is a critical component to thoroughly investigate neural interactions and brain dynamics from freely moving animals. Recent researches have shown the feasibility of simultaneously recording from hundreds of neurons and suggested that the ability of recording a larger number of neurons results in better signal quality. This massive recording inevitably demands a large amount of data transfer. For example, recording 2000 neurons while keeping the signal fidelity ( > 12 bit, > 40 KS/s per neuron) needs approximately a 1-Gb/s data link. Designing a wireless data telemetry system to support such (or higher) data rate while aiming to lower the power consumption of an implantable device imposes a grand challenge on neuroscience community. In this paper, we present a wireless gigabit data telemetry for future large-scale neural recording interface. This telemetry comprises of a pair of low-power gigabit transmitter and receiver operating at 60 GHz, and establishes a short-distance wireless link to transfer the massive amount of neural signals outward from the implanted device. The transmission distance of the received neural signal can be further extended by an externally rendezvous wireless transceiver, which is less power/heat-constraint since it is not at the immediate proximity of the cortex and its radiated signal is not seriously attenuated by the lossy tissue. The gigabit data link has been demonstrated to achieve a high data rate of 6 Gb/s with a bit-error-rate of 10(-12) at a transmission distance of 6 mm, an applicable separation between transmitter and receiver. This high data rate is able to support thousands of recording channels while ensuring a low energy cost per bit of 2.08 pJ/b.

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“…From the emitted pulse magnitude (0.95 V peak ) and the voltage sensitivity (1.7 mV peak ), the maximum communication range is evaluated to 2.36 m using (14) with G a = 3 dB and M = 6 dB. This gives additional fade margin since 1.5 m is sufficient for WBAN applications.…”

Section: Overviewmentioning

confidence: 99%