A 5 Gb/s 8×8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200 MHz LVDS interface

Abstract

The switch element (SE) is a 622Mb/s, 8 x 8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5Gbps bandwidth, supporting 5 &OS classes delay priority and link-by-link multicast. Up to a 32x32 switch with 2OGbps bandwidth can be configured using multiple SEs and distributor/ arbiter (DA) LSIs. Figure 1 shows the logical queue structure realized in SE. Since the best-effort classes will require much larger per-link buffer than that in SE, the SE can dedicate a small-cell buffer to each class and link, and feed the buffer congestion status signals back to switch access (SA) LSIs that use the expandable per link huge buffer memories. As a result of throughput simulations and chip size consideration, the 64-cell buffer per class, which corresponds to the total buffer size of 320 is selected. Link-by-link multicast function is supported using a shift register type address generator. Figure 2 shows the block diagram of SE. The input cell interfaces establish bit synchronization and cell synchronization, and transform cell data bit-width from 4b to 128b. The routing information is extracted from the cell header. The control logic contains cell counters, threshold registers and comparators. The routing information is transferred to the control logic to decide the cell to be received. The cell data is written to and read from the cell buffer with 128b in parallel sequentially from link0 to link7. Readwrite addresses of the cell buffer are controlled by a shift register type address generator using the information of cell counters and flowcontrol signals received from DA or SA. The control logic generates flow-control signals in time-multiplexed fashion to upstream LSIs using flow-control signals received from the downstream LSIs, and the status of the SE cell counters to avoid the cell buffer overflow. The output cell interfaces transform the bit-width from 128b to 4b. Finally, LVDS output buffers convert the level of output cells from CMOS to LVDS.Each link to or from the SE consists of 5 pairs of LVDS buffers4b data and l b clock. LVDS interfaces have the following advantages: 1) low-power consumption a t high-speed operation, 2) high CMRR and low EMI, 3) low-cost, 4) small-signal distortion, and 5 ) few level conversion ICs through backplanes and PCBs. Figure 3 SE.shows the schematic diagram of LVDS driver and receiver for the The shift-register type address generator shown in Figure 4a has a dedicated structure for readwrite address management of the cell buffer. The shift register is more advantageous in implementing the multicast function than the linked-list because unicast cells and multicast cells can be handled in the same way. Only one clock period is needed to enqueue a multicast cell for any combination of output links. The address generator in the SE has 320 entries, each with 8b for the output link map, l b for the multicast identifier, 3b for the class of delay priority, 9b for the address pointer to the shared buffer and l b for the address pointer parity.Since each data line ...

Design of a Low-Power CMOS LVDS I/O Interface Circuit

“…The operation speed of the LVDS is more sensitive to the receiver than the driver [6]. To enhance the LVDS performance, it is essential to design the high speed and low power LVDS receiver.…”

“…One of the effective solutions to multi-giga-bit transmission is LVDS (low-voltage differential signaling) which possesses significant advantages such as fast data rate and good energy efficiency by means of reducing signal swing on the wire [2][3][4]. Defined in LVDS standards specification, it is the most common differential interface [4][5][6][7]. The standard only specifies the electrical characteristics of drivers and receiver suitable for LVDS applications.…”

Design and realization of 1.3 Gb/s off-chip transmission circuitry using 0.35 μm CMOS technology

“…1 LVDS architecture with a only one termination resistor at the receiver end; and b termination resistors at both ends differential traces was also included in the simulation. Model order reduction (MOR) technique with a total number of 30 poles up to 10 GHz was adopted for equivalent circuit extraction with passivity enforced for all the frequency values and proper inclusion of eigen-values [13]. Figure 2 shows the comparison between the corresponding S-parameters of the extracted circuit model and that obtained from the direct electromagnetic analysis with an accuracy level of 1.00e-06 achieved.…”

Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

“…As shown in Fig. 1, the on-chip clock recovery circuit (Rx) considers multi-stage architectures usually comprised by a front-end differential amplifier and an optional differentialto-single (D2S) conversion, which can operate in both voltage [4] or current modes [5]- [7], followed by a back-end output digital buffer -in case that the D2S stage is omitted, its functionality is directly done by the output digital buffer [3], but this approach could imply a significant degradation of performance for a given power consumption budget. In case of ultra-low jitter low-power applications, the use of a dedicated D2S stage is mandatory.…”