A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3–22 GHz applications

Zhang, Yanlong; Zhang, Yiqi; Li, Zhenrong; Ren, Xueshi; Wang, Bo; Jing, Kai; Qi, Zengwei

doi:10.1016/j.mejo.2014.02.013

Cited by 11 publications

(17 citation statements)

References 19 publications

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“…The Resistor values of the attenuator circuits can be calculated by two-port network analysis [12]. Conventional switched T-bridge attenuator with reference and attenuation state is shown in Fig.…”

Section: Circuit Designmentioning

confidence: 99%

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4-Bit Ka Band Sige Bicmos Digital Step Attenuator

Sarfraz¹,

Liu²,

Ullah³

et al. 2017

PIER C

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Abstract-This paper presents a Ka-band 4-bit BiCMOS digital step attenuator with maximum attenuation of 7.5 dB (16 states). The proposed attenuator design is based on switched T-bridge network including phase correction network and is fabricated in 0.13 µm SiGe BiCMOS technology. Attenuator with phase correction structure shows root mean square (RMS) amplitude errors < 0.8 dB at 31 to 33 GHz and the RMS insertion phase varying from 2.8 • to 5.8 • over 31-33 GHz. The measured insertion loss is 19 dB and total chip size including pad is 1.92 × 0.4 mm 2 .

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Section: Circuit Designmentioning

confidence: 99%

“…In order to have no transmission phase difference, it is important to satisfy the following condition [1,12] ∆∅ =∅ A − ∅ R = 0…”

Section: Circuit Designmentioning

confidence: 99%

4-Bit Ka Band Sige Bicmos Digital Step Attenuator

Sarfraz¹,

Liu²,

Ullah³

et al. 2017

PIER C

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“…The inductor L S at series branch is used to compensate the phase lead of the attenuation state to the reference state due to the parasitic capacitance of the MOS switches [4] and broaden the operational band. The MOS switch M1 at series branch involves a channal shunt resistor, R b1 , to minimize insertion loss [5]. In addition, this resistor can minimize the capacitance seeing from the output, which can lower the insertion phase [5].…”

Section: Design Of Proposed Attenuatormentioning

confidence: 99%

“…The MOS switch M1 at series branch involves a channal shunt resistor, R b1 , to minimize insertion loss [5]. In addition, this resistor can minimize the capacitance seeing from the output, which can lower the insertion phase [5]. Although the 128 ( 2 7 ) states can be realized with switching the 7 control terminals from K1 to K7, the best one of states at each attenuaion amplitude will be chosen.…”

Section: Design Of Proposed Attenuatormentioning

confidence: 99%

“…The advanced CMOS process provides the possibility to achieve passive attenuators. The step attenuators implemented with resistive networks and switches are of high insertion loss and large insertion phase [3,4,5,6], while the distributed attenuators often perform better in lower insertion loss and lower phase distortion [2,7]. As the on-chip transmission lines consume large chip area when used to implement an attenuator with a large attenuation range, the applications of distributed attenuators are limited.…”

Section: Introductionmentioning

confidence: 99%

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A CMOS semi-distributed step attenuator with low insertion loss and low phase distortion

Zhang¹,

Zhang²,

Li³

et al. 2014

IEICE Electron. Express

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A semi-distributed step attenuator with low insertion loss and low phase distortion is presented with 0.18 µm BiCMOS process, which is implemented with a step distributed attenuator for 0-7 dB attenuation with low insertion loss and two :-type switched resistive attenuation modules for large attenuation amplitude. The proposed attenuator has a maximum attenuation range of 0-31 dB with 1 dBincrease at the frequency range of 10-20 GHz and involves less than 8.6 dB of insertion loss. The RMS amplitude error and insertion phase at each attenuation state are less than 0.6 dB and 3°, respectively.

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