A 5.8-GHz High-Frequency Resolution Digitally Controlled Oscillator Using the Difference Between Inversion and Accumulation Mode Capacitance of pMOS Varactors

Yoo, Sang-Sun; Choi, Yong-Chang; Song, Hong-Joo; Park, Seung-Chan; Park, Jeong-Ho; Yoo, Hyung-Joun

doi:10.1109/tmtt.2010.2095426

Cited by 27 publications

(13 citation statements)

References 15 publications

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“…The differential MOS varactor is also used for fine frequency tuning. Fine capacitance can be effectively implemented by using the capacitance difference in accumulation mode and inversion mode of the differential MOS varactor [7].…”

Section: B Digitally Controlled Oscillatormentioning

confidence: 99%

A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS

Park¹,

Kim²,

Lee³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in 0.18 µm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 3.5 mm 2 . The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

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Section: B Digitally Controlled Oscillatormentioning

confidence: 99%

A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS

Park¹,

Kim²,

Lee³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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“…Active capacitor is also used for the fine frequency tuning. Fine capacitance can be effectively implemented by using the capacitance difference in accumulation mode and inversion mode of active capacitor [4].…”

Section: On-chip Solenoid Inductormentioning

confidence: 99%

A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

Park¹,

Kim²,

Lee³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a wide band, fineresolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 µm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 µm process and the die area of the solenoid inductor is 0.013 mm 2 . The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

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“…2(a) shows the oppositely-coupled pMOS capacitor pair. The pair results in a smaller difference of the switchable capacitance in the DCO than that in conventional oscillator [3]. If the control voltage (V c ) is 0 (OFF-state), M 1 operates in the depletion region and M 2 operates in the inversion region.…”

Section: Effective Capacitance Analysismentioning

confidence: 99%

“…The phase noise of the DCO is a function of the frequency resolution, which is determined by the unit switchable capacitance [1], and as the frequency resolution becomes finer, the phase noise becomes accordingly lower. Some researchers have suggested high resolution DCO design methods [2]~ [3], including the use of oppositely-coupled pMOS capacitor pairs [3]. A DCO that uses oppositelycoupled pMOS capacitor pairs exploits the differences between the accumulation region and inversion region capacitances of the pMOS capacitor.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Effect of capacitor nonlinearity on the oscillation frequency of a digitally-controlled oscillator using oppositely-coupled PMOS capacitor pairs

Park

Yoo

Cho

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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Contrary to conventional digitally controlled oscillators, frequency inversion is observed in a digitally controlled oscillator (DCO) using oppositely-coupled pMOS capacitor pairs. This is due to the nonlinearity of the capacitor. In this work, the effect of the capacitor nonlinearity on the oscillation frequency is analyzed and applied to the DCO to explain the frequency inversion. A 4.8 GHz DCO for verifying the method is fabricated with a 0.18-μm CMOS process and measured. Measurements reveal the frequency inversion clearly and show very fine frequency resolution of 76 kHz, corresponding to a capacitance change of 26 aF.

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A 5.8-GHz High-Frequency Resolution Digitally Controlled Oscillator Using the Difference Between Inversion and Accumulation Mode Capacitance of pMOS Varactors

Cited by 27 publications

References 15 publications

A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS

A 12 mW ADPLL Based G/FSK Transmitter for Smart Utility Network in 0.18 ㎛ CMOS

A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

Effect of capacitor nonlinearity on the oscillation frequency of a digitally-controlled oscillator using oppositely-coupled PMOS capacitor pairs

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